To realize the high speed and low power CMOS Phase Locked Loop, we have developed new components of PLL: VCO and PFD. In the VCO, high speed and low power is realized with source coupled inverter pairs in the single loop three gate ring oscillator. And in the PFD, low power and small chip area are realized with the dynamic inverter. And with the simple design adjustment, both reduction of dead zone and immunity of current fluctuation at "O" output are implemented in Charge Pump. A fully CMOS PLL with these components have been designed with 0.8µ CMOS. At 622MHz operation, the power dissipation of 18mW is achieved by SPICE simulation.

In order to investigate the jitter characteristics of PLLs for practical applications, we have developed a computer simulation program of PLL, which can deal with arbitrary patterns both of data and jitters, as well as a conceivable nonlinearity of the circuit performance. We used a time-domain method, namely, we solved the state equation of a charge pump type PLL with a constant time step. The jitter transfer characteristics of a conventional PLL were calculated for periodic input data patterns with sinusoidal jitters. The result agreed fairly well with the corresponding experiments. And we have revealed that an ordinary PD (Phase Detector), which detects the phase difference between input and VCO signals at only rising edges, shows the folded jitter transfer characteristics at the half of the equivalent frequency of the input signal. This folded jitter characteristics increases the total jitter for long successive '1' or '0' data patterns, because of their low equivalent sampling frequency, and might increase the jitter even for the random data patterns. Based on simulation results, we devised an improved phase detector for PLL having a low jitter characteristics. And we also applied the simulation to an FDD (Frequency Difference Detector) type fast pull-in PLL which we have proposed recently, and obtained that the jitter of it was smaller than that of a conventional PLL by 25% for PRBS (pseudo random bit sequence) NRZ code.