To realize the high speed and low power CMOS Phase Locked Loop, we have developed new components of PLL: VCO and PFD. In the VCO, high speed and low power is realized with source coupled inverter pairs in the single loop three gate ring oscillator. And in the PFD, low power and small chip area are realized with the dynamic inverter. And with the simple design adjustment, both reduction of dead zone and immunity of current fluctuation at "O" output are implemented in Charge Pump. A fully CMOS PLL with these components have been designed with 0.8µ CMOS. At 622MHz operation, the power dissipation of 18mW is achieved by SPICE simulation.

This paper describes low voltage write driver with pulse adding circuit. The presented write driver is constructed from the main switch circuit with impedance matching and pulse adding circuits and a timing generator. The main switch circuit is voltage type driver with matching resisters for flexible lines between a write driver and a write head. For 1.2 Gbps operation, the flexible lines have to be treated as transmission lines. Furthermore, to achieve steep rise/fall edge, the pulse adding circuits to generate double of supply voltage, +3.3/-3 V, at rise/fall edge have been developed. The write driver was implemented using 0.35 µm BiCMOS process. The die size is 1.2 mm0.6 mm and the measured results achieved tr/tf of less than 0.25 ns, tp of 0.5 ns and Ip of 73 mA.