A Low Power 622MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD

Hiroyasu YOSHIZAWA; Kenji TANIGUCHI; Hiroyuki SHIRAHAMA; Kenichi NAKASHI

A Low Power 622MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD

Hiroyasu YOSHIZAWA, Kenji TANIGUCHI, Hiroyuki SHIRAHAMA, Kenichi NAKASHI

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To realize the high speed and low power CMOS Phase Locked Loop, we have developed new components of PLL: VCO and PFD. In the VCO, high speed and low power is realized with source coupled inverter pairs in the single loop three gate ring oscillator. And in the PFD, low power and small chip area are realized with the dynamic inverter. And with the simple design adjustment, both reduction of dead zone and immunity of current fluctuation at "O" output are implemented in Charge Pump. A fully CMOS PLL with these components have been designed with 0.8µ CMOS. At 622MHz operation, the power dissipation of 18mW is achieved by SPICE simulation.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.6 pp.1015-1020

Publication Date: 1997/06/25

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Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))

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Hiroyasu YOSHIZAWA, Kenji TANIGUCHI, Hiroyuki SHIRAHAMA, Kenichi NAKASHI, "A Low Power 622MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD" in IEICE TRANSACTIONS on Fundamentals, vol. E80-A, no. 6, pp. 1015-1020, June 1997, doi: .
Abstract: To realize the high speed and low power CMOS Phase Locked Loop, we have developed new components of PLL: VCO and PFD. In the VCO, high speed and low power is realized with source coupled inverter pairs in the single loop three gate ring oscillator. And in the PFD, low power and small chip area are realized with the dynamic inverter. And with the simple design adjustment, both reduction of dead zone and immunity of current fluctuation at "O" output are implemented in Charge Pump. A fully CMOS PLL with these components have been designed with 0.8µ CMOS. At 622MHz operation, the power dissipation of 18mW is achieved by SPICE simulation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_6_1015/_p

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@ARTICLE{e80-a_6_1015,
author={Hiroyasu YOSHIZAWA, Kenji TANIGUCHI, Hiroyuki SHIRAHAMA, Kenichi NAKASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Low Power 622MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD},
year={1997},
volume={E80-A},
number={6},
pages={1015-1020},
abstract={To realize the high speed and low power CMOS Phase Locked Loop, we have developed new components of PLL: VCO and PFD. In the VCO, high speed and low power is realized with source coupled inverter pairs in the single loop three gate ring oscillator. And in the PFD, low power and small chip area are realized with the dynamic inverter. And with the simple design adjustment, both reduction of dead zone and immunity of current fluctuation at "O" output are implemented in Charge Pump. A fully CMOS PLL with these components have been designed with 0.8µ CMOS. At 622MHz operation, the power dissipation of 18mW is achieved by SPICE simulation.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - A Low Power 622MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1015
EP - 1020
AU - Hiroyasu YOSHIZAWA
AU - Kenji TANIGUCHI
AU - Hiroyuki SHIRAHAMA
AU - Kenichi NAKASHI
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1997
AB - To realize the high speed and low power CMOS Phase Locked Loop, we have developed new components of PLL: VCO and PFD. In the VCO, high speed and low power is realized with source coupled inverter pairs in the single loop three gate ring oscillator. And in the PFD, low power and small chip area are realized with the dynamic inverter. And with the simple design adjustment, both reduction of dead zone and immunity of current fluctuation at "O" output are implemented in Charge Pump. A fully CMOS PLL with these components have been designed with 0.8µ CMOS. At 622MHz operation, the power dissipation of 18mW is achieved by SPICE simulation.
ER -