We produced a double-layer thin-film heater to detrap magnetic flux in a SQUID sensor. The heater is integrated on a sensor chip, and consists of a lower resistor layer and an upper superconducting layer to cancel the magnetic field produced by the heater current. The SQUID sensor is cooled below its critical temperature with a temperature gradient to detrap the flux completely. To make the gradient, we had to decrease heater power to zero over an interval exceeding 10-4 second in our experiment, which is almost equal to the sensor chip's thermal time constant. The integrated heater effectively controls the temperature profile and detraps flux in the sensor.

The paper provides an overview of the circuit techniques for CMOS high-speed I/Os, focusing on the design issues in sub-100 nm standard CMOS. First, we describe the evolution of CMOS high-speed I/O since it appeared in mid 90's. In our view, the surge in the I/O bandwidth we experienced from the mid 90's to the present was driven by the continuous improvement of the CMOS IC performance. As a result, CMOS high-speed I/O has covered the data rate ranging from 2.5 Gb/s to 10 Gb/s, and now is heading for 40 Gb/s and beyond. To meet the speed requirements, an optimum choice of the transceiver architecture and its building blocks are crucial. We pick the most critical building blocks such as the decision circuit and the multiplexors and give detailed explanation of their designs. We describe the low-voltage operation of the high-speed I/O in view of reducing the power consumption. An example of a 90-nm CMOS 2.5 Gb/s transceiver operating off a 0.8 V power supply will be described. Operability at 0.8 V ensures that the circuits will not become obsolescent, even below the 60 nm process node.