IEICE TRANSACTIONS on Electronics
Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies
Summary :
The paper provides an overview of the circuit techniques for CMOS high-speed I/Os, focusing on the design issues in sub-100 nm standard CMOS. First, we describe the evolution of CMOS high-speed I/O since it appeared in mid 90's. In our view, the surge in the I/O bandwidth we experienced from the mid 90's to the present was driven by the continuous improvement of the CMOS IC performance. As a result, CMOS high-speed I/O has covered the data rate ranging from 2.5 Gb/s to 10 Gb/s, and now is heading for 40 Gb/s and beyond. To meet the speed requirements, an optimum choice of the transceiver architecture and its building blocks are crucial. We pick the most critical building blocks such as the decision circuit and the multiplexors and give detailed explanation of their designs. We describe the low-voltage operation of the high-speed I/O in view of reducing the power consumption. An example of a 90-nm CMOS 2.5 Gb/s transceiver operating off a 0.8 V power supply will be described. Operability at 0.8 V ensures that the circuits will not become obsolescent, even below the 60 nm process node.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.3 pp.300-313
- Publication Date
- 2006/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.3.300
- Type of Manuscript
- Special Section INVITED PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Hirotaka TAMURA, Masaya KIBUNE, Hisakatsu YAMAGUCHI, Kouichi KANDA, Kohtaroh GOTOH, Hideki ISHIDA, Junji OGAWA, "Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 3, pp. 300-313, March 2006, doi: 10.1093/ietele/e89-c.3.300.
Abstract: The paper provides an overview of the circuit techniques for CMOS high-speed I/Os, focusing on the design issues in sub-100 nm standard CMOS. First, we describe the evolution of CMOS high-speed I/O since it appeared in mid 90's. In our view, the surge in the I/O bandwidth we experienced from the mid 90's to the present was driven by the continuous improvement of the CMOS IC performance. As a result, CMOS high-speed I/O has covered the data rate ranging from 2.5 Gb/s to 10 Gb/s, and now is heading for 40 Gb/s and beyond. To meet the speed requirements, an optimum choice of the transceiver architecture and its building blocks are crucial. We pick the most critical building blocks such as the decision circuit and the multiplexors and give detailed explanation of their designs. We describe the low-voltage operation of the high-speed I/O in view of reducing the power consumption. An example of a 90-nm CMOS 2.5 Gb/s transceiver operating off a 0.8 V power supply will be described. Operability at 0.8 V ensures that the circuits will not become obsolescent, even below the 60 nm process node.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.3.300/_p
Copy
@ARTICLE{e89-c_3_300,
author={Hirotaka TAMURA, Masaya KIBUNE, Hisakatsu YAMAGUCHI, Kouichi KANDA, Kohtaroh GOTOH, Hideki ISHIDA, Junji OGAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies},
year={2006},
volume={E89-C},
number={3},
pages={300-313},
abstract={The paper provides an overview of the circuit techniques for CMOS high-speed I/Os, focusing on the design issues in sub-100 nm standard CMOS. First, we describe the evolution of CMOS high-speed I/O since it appeared in mid 90's. In our view, the surge in the I/O bandwidth we experienced from the mid 90's to the present was driven by the continuous improvement of the CMOS IC performance. As a result, CMOS high-speed I/O has covered the data rate ranging from 2.5 Gb/s to 10 Gb/s, and now is heading for 40 Gb/s and beyond. To meet the speed requirements, an optimum choice of the transceiver architecture and its building blocks are crucial. We pick the most critical building blocks such as the decision circuit and the multiplexors and give detailed explanation of their designs. We describe the low-voltage operation of the high-speed I/O in view of reducing the power consumption. An example of a 90-nm CMOS 2.5 Gb/s transceiver operating off a 0.8 V power supply will be described. Operability at 0.8 V ensures that the circuits will not become obsolescent, even below the 60 nm process node.},
keywords={},
doi={10.1093/ietele/e89-c.3.300},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies
T2 - IEICE TRANSACTIONS on Electronics
SP - 300
EP - 313
AU - Hirotaka TAMURA
AU - Masaya KIBUNE
AU - Hisakatsu YAMAGUCHI
AU - Kouichi KANDA
AU - Kohtaroh GOTOH
AU - Hideki ISHIDA
AU - Junji OGAWA
PY - 2006
DO - 10.1093/ietele/e89-c.3.300
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2006
AB - The paper provides an overview of the circuit techniques for CMOS high-speed I/Os, focusing on the design issues in sub-100 nm standard CMOS. First, we describe the evolution of CMOS high-speed I/O since it appeared in mid 90's. In our view, the surge in the I/O bandwidth we experienced from the mid 90's to the present was driven by the continuous improvement of the CMOS IC performance. As a result, CMOS high-speed I/O has covered the data rate ranging from 2.5 Gb/s to 10 Gb/s, and now is heading for 40 Gb/s and beyond. To meet the speed requirements, an optimum choice of the transceiver architecture and its building blocks are crucial. We pick the most critical building blocks such as the decision circuit and the multiplexors and give detailed explanation of their designs. We describe the low-voltage operation of the high-speed I/O in view of reducing the power consumption. An example of a 90-nm CMOS 2.5 Gb/s transceiver operating off a 0.8 V power supply will be described. Operability at 0.8 V ensures that the circuits will not become obsolescent, even below the 60 nm process node.
ER -
English
