Conventional algorithms for the joint estimation of carrier frequency offset (CFO) and I/Q imbalance no longer work when the I/Q imbalance depends on the frequency. In order to correct the imbalance across many frequencies, the compensator needed is a filter as opposed to a simple gain and phase compensator. Although, algorithms for estimating the optimal coefficients of this filter exist, their complexity is too high for hardware implementation. In this paper we present a new low complexity algorithm for joint estimation of CFO and frequency dependent I/Q imbalance. For the first part, we derive the estimation scheme using the linear least squares algorithm and examine its floating point performance compared to conventional algorithms. We show that the proposed algorithm can completely eliminate BER floor caused by CFO and I/Q imbalance at a lesser complexity compared to conventional algorithms. For the second part, we examine the hardware complexity in fixed point hardware and latency of the proposed algorithm. Based on BER performance, the circuit needs a wordlength of at least 16 bits in order to properly estimate CFO and I/Q imbalance. In this configuration, the circuit is able to achieve a maximum speed of 115.9 MHz in a Virtex 5 FPGA.

Thanks to the achievements in wireless technology, maximum data rate of wireless LAN systems was rapidly increased recently. As a key part of the WEP and the WPA security for the wireless LAN system, throughput of RC4 must be significantly improved also. This paper proposes two high throughput RC4 architectures. The first one is a RAM-based RC4 using a single of 256-byte tri-port RAM to store the S-box. The core generates 4bits of ciphering key per clock cycle. This paper also proves that 4bits/cycle is the maximum throughput can be achieved by a RAM-based RC4 circuit. The second architecture is a Register-based M-byte RC4 that uses a set of registers to store the S-box. It is able to generate multiple bytes of ciphering key per clock cycle, and is proposed as a novel solution for designing extremely high throughput RC4 core for future WLAN systems. Base on this proposal, a 4-byte RC4 core is developed (M=4). The synthesis results in 90nm ASIC show that: As the same throughput's requirement, the proposed RAM-based and Register-based RC4 can respectively save 60% and 50% of power consumption as compare to that of the most recently works. Moreover, the proposed Register-based design is the best candidate for achieving high throughput at low frequency.