IEICE TRANSACTIONS on Fundamentals
Hardware Design of Multi Gbps RC4 Stream Cipher
Summary :
Thanks to the achievements in wireless technology, maximum data rate of wireless LAN systems was rapidly increased recently. As a key part of the WEP and the WPA security for the wireless LAN system, throughput of RC4 must be significantly improved also. This paper proposes two high throughput RC4 architectures. The first one is a RAM-based RC4 using a single of 256-byte tri-port RAM to store the S-box. The core generates 4bits of ciphering key per clock cycle. This paper also proves that 4bits/cycle is the maximum throughput can be achieved by a RAM-based RC4 circuit. The second architecture is a Register-based M-byte RC4 that uses a set of registers to store the S-box. It is able to generate multiple bytes of ciphering key per clock cycle, and is proposed as a novel solution for designing extremely high throughput RC4 core for future WLAN systems. Base on this proposal, a 4-byte RC4 core is developed (M=4). The synthesis results in 90nm ASIC show that: As the same throughput's requirement, the proposed RAM-based and Register-based RC4 can respectively save 60% and 50% of power consumption as compare to that of the most recently works. Moreover, the proposed Register-based design is the best candidate for achieving high throughput at low frequency.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.11 pp.2120-2127
- Publication Date
- 2013/11/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E96.A.2120
- Type of Manuscript
- Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
- Category
- VLSI Design Technology and CAD
Authors
Thi Hong TRAN
Kyushu Institute of Technology
Leonardo LANANTE, Jr.
Kyushu Institute of Technology
Yuhei NAGAO
Kyushu Institute of Technology
Hiroshi OCHI
Kyushu Institute of Technology
Keyword
RC4, encryption, WEP, WPA, IEEE 802.11ac
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Thi Hong TRAN, Leonardo LANANTE, Jr., Yuhei NAGAO, Hiroshi OCHI, "Hardware Design of Multi Gbps RC4 Stream Cipher" in IEICE TRANSACTIONS on Fundamentals,
vol. E96-A, no. 11, pp. 2120-2127, November 2013, doi: 10.1587/transfun.E96.A.2120.
Abstract: Thanks to the achievements in wireless technology, maximum data rate of wireless LAN systems was rapidly increased recently. As a key part of the WEP and the WPA security for the wireless LAN system, throughput of RC4 must be significantly improved also. This paper proposes two high throughput RC4 architectures. The first one is a RAM-based RC4 using a single of 256-byte tri-port RAM to store the S-box. The core generates 4bits of ciphering key per clock cycle. This paper also proves that 4bits/cycle is the maximum throughput can be achieved by a RAM-based RC4 circuit. The second architecture is a Register-based M-byte RC4 that uses a set of registers to store the S-box. It is able to generate multiple bytes of ciphering key per clock cycle, and is proposed as a novel solution for designing extremely high throughput RC4 core for future WLAN systems. Base on this proposal, a 4-byte RC4 core is developed (M=4). The synthesis results in 90nm ASIC show that: As the same throughput's requirement, the proposed RAM-based and Register-based RC4 can respectively save 60% and 50% of power consumption as compare to that of the most recently works. Moreover, the proposed Register-based design is the best candidate for achieving high throughput at low frequency.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.2120/_p
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@ARTICLE{e96-a_11_2120,
author={Thi Hong TRAN, Leonardo LANANTE, Jr., Yuhei NAGAO, Hiroshi OCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hardware Design of Multi Gbps RC4 Stream Cipher},
year={2013},
volume={E96-A},
number={11},
pages={2120-2127},
abstract={Thanks to the achievements in wireless technology, maximum data rate of wireless LAN systems was rapidly increased recently. As a key part of the WEP and the WPA security for the wireless LAN system, throughput of RC4 must be significantly improved also. This paper proposes two high throughput RC4 architectures. The first one is a RAM-based RC4 using a single of 256-byte tri-port RAM to store the S-box. The core generates 4bits of ciphering key per clock cycle. This paper also proves that 4bits/cycle is the maximum throughput can be achieved by a RAM-based RC4 circuit. The second architecture is a Register-based M-byte RC4 that uses a set of registers to store the S-box. It is able to generate multiple bytes of ciphering key per clock cycle, and is proposed as a novel solution for designing extremely high throughput RC4 core for future WLAN systems. Base on this proposal, a 4-byte RC4 core is developed (M=4). The synthesis results in 90nm ASIC show that: As the same throughput's requirement, the proposed RAM-based and Register-based RC4 can respectively save 60% and 50% of power consumption as compare to that of the most recently works. Moreover, the proposed Register-based design is the best candidate for achieving high throughput at low frequency.},
keywords={},
doi={10.1587/transfun.E96.A.2120},
ISSN={1745-1337},
month={November},}
Copy
TY - JOUR
TI - Hardware Design of Multi Gbps RC4 Stream Cipher
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2120
EP - 2127
AU - Thi Hong TRAN
AU - Leonardo LANANTE
AU - Jr.
AU - Yuhei NAGAO
AU - Hiroshi OCHI
PY - 2013
DO - 10.1587/transfun.E96.A.2120
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2013
AB - Thanks to the achievements in wireless technology, maximum data rate of wireless LAN systems was rapidly increased recently. As a key part of the WEP and the WPA security for the wireless LAN system, throughput of RC4 must be significantly improved also. This paper proposes two high throughput RC4 architectures. The first one is a RAM-based RC4 using a single of 256-byte tri-port RAM to store the S-box. The core generates 4bits of ciphering key per clock cycle. This paper also proves that 4bits/cycle is the maximum throughput can be achieved by a RAM-based RC4 circuit. The second architecture is a Register-based M-byte RC4 that uses a set of registers to store the S-box. It is able to generate multiple bytes of ciphering key per clock cycle, and is proposed as a novel solution for designing extremely high throughput RC4 core for future WLAN systems. Base on this proposal, a 4-byte RC4 core is developed (M=4). The synthesis results in 90nm ASIC show that: As the same throughput's requirement, the proposed RAM-based and Register-based RC4 can respectively save 60% and 50% of power consumption as compare to that of the most recently works. Moreover, the proposed Register-based design is the best candidate for achieving high throughput at low frequency.
ER -
English
