Clock gating is the insertion of control signal for registers to switch off unnecessary clock signals selectively without violating the functional correctness of the original design so as to reduce the dynamic power consumption. Commercial EDA tools usually have a mechanism to generate clock gating logic based on the structural method where the control signals specified by designers are used, and the effectiveness of the clock gating depends on the specified control signals. In the research, we focus on the automatic clock gating logic generation and propose a method based on the candidate extraction and control signal selection. We formalize the control signal selection using linear formulae and devise an optimization method based on BDD. The method is effective for circuits with a lot of shared candidates by different registers. The method is applied to counter circuits to check the co-relation with power simulation results and a set of benchmark circuits. 19.1-71.9% power reduction has been found on counter circuitsafter layout and 2.3-18.0% cost reduction on benchmark circuits.

In this article, we present a scattered pilot aided channel estimation and tracking technique for MIMO-OFDM systems. First we extend Li's estimation algorithm to scattered pilot-aided case. Then a scattered pilot-aided tracking scheme is developed to track the time-varying MIMO channel. The algorithms we present reduce the system overhead and channel estimation complexity to a low level with acceptable performance degradation. Simulations of a MIMO-OFDM system with four-transmit and four-receive antennas show that the new algorithm has better performance than Li's algorithm in time-varying MIMO channels.

Through novel rotation writing method of Bragg grating in multicore fiber, its strain vector characteristics are analyzed. The relation between the rotation angle and the strain curvature sensitivity is obtained. Reconstruction of strain vector is verified.

Clock gating is supported by commercial tools as a power optimization feature based on the guard signal described in HDL (structural method). However, the identification of control signals for gated registers is hard and designer-intensive work. Besides, since the clock gating cells also consume power, it is imperative to minimize the number of inserted clock gating cells and their switching activities for power optimization. In this paper, we propose an automatic multi-stage clock gating algorithm with ILP (Integer Linear Programming) formulation, including clock gating control candidate extraction, constraints construction and optimum control signal selection. By multi-stage clock gating, unnecessary clock pulses to clock gating cells can be avoided by other clock gating cells, so that the switching activity of clock gating cells can be reduced. We find that any multi-stage control signals are also single-stage control signals, and any combination of signals can be selected from single-stage candidates. The proposed method can be applied to 3 or more cascaded stages. The multi-stage clock gating optimization problem is formulated as constraints in LP format for the selection of cascaded clock-gating order of multi-stage candidate combinations, and a commercial ILP solver (IBM CPLEX) is applied to obtain the control signals for each register with minimum switching activity. Those signals are used to generate a gate level description with guarded registers from original design, and a commercial synthesis and layout tools are applied to obtain the circuit with multi-stage clock gating. For a set of benchmark circuits and a Low Density Parity Check (LDPC) Decoder (6.6k gates, 212 F.F.s), the proposed method is applied and actual power consumption is estimated using Synopsys NanoSim after layout. On average, 31% actual power reduction has been obtained compared with original designs with structural clock gating, and more than 10% improvement has been achieved for some circuits compared with single-stage optimization method. CPU time for optimum multi-stage control selection is several seconds for up to 25k variables in LP format. By applying the proposed clock gating, area can also be reduced since the multiplexors controlling register inputs are eliminated.

This paper proposes a SNR estimation scheme based on Gibbs sampler. This scheme can estimate SNR using a very short received sequence, and does not require any prior information of the transmitted symbol. Compared with the existing estimators, the performance of this method is better when real SNR is larger than 5 dB in both single path channel and multi-path channel.

Dynamic spectrum access has become a focal issue recently, in which identifying the available spectrum plays a rather important role. Lots of work has been done concerning secondary user (SU) synchronously accessing primary user's (PU's) network. However, on one hand, SU may have no idea about PU's communication protocols; on the other, it is possible that communications among PU are not based on synchronous scheme at all. In order to address such problems, this paper advances a strategy for SU to search available spectrums with asynchronous MAC-layer sensing. With this method, SUs need not know the communication mechanisms in PU's network when dynamically accessing. We will focus on four aspects: 1) strategy for searching available channels; 2) vacating strategy when PUs come back; 3) estimation of channel parameters; 4) impact of SUs' interference on PU's data rate. The simulations show that our search strategy not only can achieve nearly 50% less interference probability than equal allocation of total search time, but also well adapts to time-varying channels. Moreover, access by our strategies can attain 150% more access time than random access. The moment matching estimator shows good performance in estimating and tracing time-varying channels.

The unfairness problem among TCP connections has been proved to be very severe in the IEEE 802.11-based wireless ad hoc networks because the hidden station problem still exists and the binary exponential backoff algorithm always favors the latest successful station. In this paper, a novel protocol, neighbor-medium-aware MAC (NEMA-MAC), is proposed to improve the TCP fairness. By adding a medium (channel) state field in the head of the traditional IEEE 802.11 MAC frame, the NEMA-MAC protocol provides a communication mechanism to resolve the hidden station problem. In addition, when a collision occurs, the new backoff algorithm makes the senders cooperatively adjust the contention window according to their local and neighbors' channel usage indexes. The simulation results show that TCP sessions can acquire satisfying fairness and increase the throughput in the NEMA-MAC-based multihop ad hoc networks.

The estimation problem of structured clutter covariance matrix (CCM) in space-time adaptive processing (STAP) for airborne radar systems is studied in this letter. By employing the prior knowledge and the persymmetric covariance structure, a new estimation algorithm is proposed based on the whitening ability of the covariance matrix. The proposed algorithm is robust to prior knowledge of different accuracy, and can whiten the observed interference data to obtain the optimal solution. In addition, the extended factored approach (EFA) is used in the optimization for dimensionality reduction, which reduces the computational burden. Simulation results show that the proposed algorithm can effectively improve STAP performance even under the condition of some errors in prior knowledge.