A novel effective channel length extraction method has been developed, which utilizes the difference between the local threshold voltage of channel region and that of external region. In this method, the dependence of external resistance on Vg is taken into account, and it is not necessary to extract Vth. It is found that the external resistance can be approximated as the linear function of Vg with Vg around Vth. For a 0.4 µm gate length LDD MOSFET, the accuracy and resolution are estimated to be less than 0.02 µm and 0.003 µm, respectively.

Low-temperature MOSFET is a promising device for future high-speed VLSI. We have developed a three-dimensional device simulator which can be used for the analysis of low-temperature deep-submicron MOSFET's. In order to improve the convergence property, the method of physical limiting on increment (PLI) was suggested. Two types of PLI, i.e., the limiting on potential increment (LPI) and the limiting on carrie-concentration increment (LCI) were showed to be very simple and effective methods for both 300 K and 77 K. Using the simulated results of COLD3, we showed the threshold variation in a low-temperature MOSFET due to the narrow channel effect can be suppressed if the device is designed according to the temperature scaling law.