An asymmetric zero correlation zone (A-ZCZ) sequence set can be regarded as a special type of ZCZ sequence set, which consists of multiple sequence subsets. Each subset is a ZCZ sequence set, and have a common zero cross-correlation zone (ZCCZ) between sequences from different subsets. This paper supplements an existing construction of A-ZCZ sequence sets and further improves the research results. Besides, a new construction of A-ZCZ sequence sets is proposed by matrices transformation. The obtained sequence sets are optimal with respect to theoretical bound, and the parameters can be chosen more flexibly, such as the number of subsets and the lengths of ZCCZ between sequences from different subsets. Moreover, as the diversity of the orthogonal matrices and the flexibility of initial matrix, more A-ZCZ sequence sets can be obtained. The resultant sequence sets presented in this paper can be applied to multi-cell quasi-synchronous code-division multiple-access (QS-CDMA) systems, to eliminate the interference not only from the same cell but also from adjacent cells.

Blocking artifact is a major limitation of DCT-based codec at low bit rates. This degradation is likely to influence the judgment of a final user. This work presents a powerful post-processing filter in the DCT frequency domain. The proposed algorithm adopts a shift block within four adjacent DCT blocks to reduce computational complexity. The artifacts resulting from quantized and de-quantized process are eliminated by slightly modifying several DCT coefficients in the shift block. Simulation results indicate that the proposed method produces the best image quality in terms of both objective and subjective metrics.

A construction of shift sequence sets is proposed. Multiple distinct shift sequence sets are obtained by changing the parameters of the shift sequences. The shift sequences satisfy the conditions that P|L and P ≥ 2, where P is the length of the shift sequences, L is the length of the zero-correlation zone or low-correlation zone (ZCZ/LCZ). Then based on these shift sequence sets, many shift distinct ZCZ/LCZ sequence sets are constructed by using interleaving technique and complex Hadamard matrices. Furthermore, the new construction is optimal under the conditions proposed in this paper. Compared with previous constructions, the proposed construction extends the number of shift distinct ZCZ/LCZ sequence sets, so that more sequence sets are obtained for multi-cell quasi-synchronous code-division multiple access (QS-CDMA) systems.

This paper is focused on discussing a low-voltage system for lightning, and in particular the testing equipment of surge arresters. Only by demonstrating the performance and applicability of arresters can we seek the most feasible and economic low-voltage solutions. After performing repeated experiments with the same testing samples, using different testing equipment, we compare the different test results in order to select the most suitable and applicable testing equipment. In addition, the basis of a surge current parameter design theory is confirmed and verified through the test results using a simple and compact Impulse Current Generator to test a wide range of samples. By performing the actual analyzes and experiments, we can understand deeply how R, L, and C affect surge current, current wave, and current wave time. The ideal testing equipment standards have been set as follows: (1) Test Voltage up to 20 kV; (2) Expand current range from 1.5 kA to 46.5 kA, with resolution 1.5 kA; and (3) Simple operational procedures.

Based on a ternary perfect sequence and a binary orthogonal matrix, the Z-periodic complementary sequence (ZPCS) sets over the 8-QAM+ constellation are constructed. The resultant sequences can be used in multi-carriers code division multiple access (MC-CDMA) systems to remove interference and increase the transmission rate. The proposed construction provides flexible choice for parameters so as to meet different requirements in the application. A construction of shift sequence sets is proposed and the number of 8-QAM ZPCS sets is extended by changing the parameters of shift sequences. As a result, more users can be accommodated in the system.

Reducing power consumption is a crucial factor making industrial designs, such as mobile SoCs, competitive. Voltage scaling (VS) is the classical yet most effective technique that contributes to quadratic power reduction. A recent design technique called activation-aware slack assignment (ASA) enhances the voltage-scaling by allocating the timing margin of critical paths with a stochastic mean-time-to-failure (MTTF) analysis. Meanwhile, such stochastic treatment of timing errors is accepted in limited application domains, such as image processing. This paper proposes a design optimization methodology that achieves a mode-wise voltage-scalable (MWVS) design guaranteeing no timing errors in each mode operation. This work formulates the MWVS design as an optimization problem that minimizes the overall power consumption considering each mode duration, achievable voltage lowering and accompanied circuit overhead explicitly, and explores the solution space with the downhill simplex algorithm that does not require numerical derivation and frequent objective function evaluations. For obtaining a solution, i.e., a design, in the optimization process, we exploit the multi-corner multi-mode design flow in a commercial tool for performing mode-wise ASA with sets of false paths dedicated to individual modes. We applied the proposed design methodology to RISC-V design. Experimental results show that the proposed methodology saves 13% to 20% more power compared to the conventional VS approach and attains 8% to 15% gain from the conventional single-mode ASA. We also found that cycle-by-cycle fine-grained false path identification reduced leakage power by 31% to 42%.

In this paper, we propose a simple, yet effective, multiuser detection scheme for a two-hop cooperative CDMAs. In phase 1, the minimum mean square error (MMSE) detector at the destination is used to identify reliable decisions of direct transmissions from the sources and return them to the relays. Then, in phase 2, based on the reliable decisions, the relays and the destination successively utilize the maximum likelihood (ML) detectors to estimate the residual symbols. Due to the destination estimating the symbols separately from direct transmissions and the relaying signals, as a result the destination does not need the information about the relays' decision performance for the construction of the ML detector. Hence, the proposed scheme is more feasible than existing approaches for practical implementation. In addition, due to the ML detectors in phase 2 only estimating the residual symbols, the number of computations performed by the ML detectors can be reduced significantly. The results of simulations and complexity analysis demonstrate the efficiency and effectiveness of the proposed scheme.

A mobile ad-hoc network (MANET) consists of a collection of wireless mobile nodes without any fixed network infrastructure. Since the mobile nodes form a constantly changing topology, the design of efficient and scalable routing protocols is a fundamental challenge in MANETs. In the current literature, position-based routing protocols are regarded as having better scalability and lower control overhead than topology-based routing protocols. Since location services are the most critical part of position-based routing protocols, we present a multi-home-region scheme, Distributed Virtual Home Region with Spatial Awareness (DVHR-SA), to improve the performance of location service in this paper. Our scheme adaptively selects different update and query procedures according to the location of a source node. The simulation results show that DVHR-SA shortens the lengths of the update, query and reply paths. Our scheme also reduces the overall network message overhead. Therefore, DVHR-SA is considerably fast and stable.

Multicore processor architectures have become ubiquitous in today's computing platforms, especially in parallel computing installations, with their power and cost advantages. While the technology trend continues towards having hundreds of cores on a chip in the foreseeable future, an urgent question posed to system designers as well as application users is whether applications can receive sufficient support on today's operating systems for them to scale to many cores. To this end, people need to understand the strengths and weaknesses on their support on scalability and to identify major bottlenecks limiting the scalability, if any. As open-source operating systems are of particular interests in the research and industry communities, in this paper we choose three operating systems (Linux, Solaris and FreeBSD) to systematically evaluate and compare their scalability by using a set of highly-focused microbenchmarks for broad and detailed understanding their scalability on an AMD 32-core system. We use system profiling tools and analyze kernel source codes to find out the root cause of each observed scalability bottleneck. Our results reveal that there is no single operating system among the three standing out on all system aspects, though some system(s) can prevail on some of the system aspects. For example, Linux outperforms Solaris and FreeBSD significantly for file-descriptor- and process-intensive operations. For applications with intensive sockets creation and deletion operations, Solaris leads FreeBSD, which scales better than Linux. With the help of performance tools and source code instrumentation and analysis, we find that synchronization primitives protecting shared data structures in the kernels are the major bottleneck limiting system scalability.

Web application second-order vulnerabilities first inject malicious code into the persistent data stores of the web server and then execute it at later sensitive operations, causing severe impact. Nevertheless, the dynamic features, the complex data propagation, and the inter-state dependencies bring many challenges in discovering such vulnerabilities. To address these challenges, we propose DISOV, a web application property graph (WAPG) based method to discover second-order vulnerabilities. Specifically, DISOV first constructs WAPG to represent data propagation and inter-state dependencies of the web application, which can be further leveraged to find the potential second-order vulnerabilities paths. Then, it leverages fuzz testing to verify the potential vulnerabilities paths. To verify the effectiveness of DISOV, we tested it in 13 popular web applications in real-world and compared with Black Widow, the state-of-the-art web vulnerability scanner. DISOV discovered 43 second-order vulnerabilities, including 23 second-order XSS vulnerabilities, 3 second-order SQL injection vulnerabilities, and 17 second-order RCE vulnerabilities. While Black Widow only discovered 18 second-order XSS vulnerabilities, with none second-order SQL injection vulnerability and second-order RCE vulnerability. In addition, DISOV has found 12 0-day second-order vulnerabilities, demonstrating its effectiveness in practice.

This paper proposes a channel estimation technique which uses a postfixed pseudo-noise (PN) sequence combined with zero padding to accurately estimate the channel impulse response for mobile orthogonal frequency division multiplexing (OFDM) communications. The major advantage of the proposed techniques is the periodical insertion of PN sequences after each OFDM symbol within the original guard interval in conventional zero-padded OFDM or within the original cyclic prefix (CP) in conventional CP-OFDM. In addition, the proposed technique takes advantage of null samples padded after the PN sequences for reducing inter-symbol interference occurring with the information detection in conventional pseudo-random-postfix OFDM. The proposed technique successfully applies either (1) least-squares algorithm with decision-directed data-assistance, (2) approximate least-squares estimation, or (3) maximum-likelihood scheme with various observation windows for the purpose of improving channel estimation performance. Some comparative simulations are given to illustrate the excellent performance of the proposed channel estimation techniques in mobile environments.

In this paper, we present a study on the activity of second harmonic generation (SHG) from mixtures of organic nonlinear materials 2-methyl-4-nitroaniline (MNA) and paranitroaniline (pNA), changing the mixing ratio over a wide range. The mixtures show a maximum SHG powder efficiency of 520 ( urea) at a mixing weight ratio of MNA/pNA=40. We also present a setup for the measurement of the powder efficiency that an integrating sphere and a small hemispherical mirror are in contact with the sample cell on the reflecting and transmitting sides, respectively. This setup is conveniently used to effectively collect the second harmonic waves radiated from organic powder samples, since the transmissivity is usually very small due to scattering. The X-ray diffraction patterns indicate that the enhanced SHG activity of the mixtures may be due to some changes of MNA molecules in the direction of the hydrogen bond, though the crystal structure is unchanged. The SHG activity of the mixtures is found to be thermostable and also not to change so much for over two months.

Two new families of balanced almost binary sequences with a single zero element of period L=2q are presented in this letter, where q=4d+1 is an odd prime number. These sequences have optimal autocorrelation value or optimal autocorrelation magnitude. Our constructions are based on cyclotomy and Chinese Remainder Theorem.

We propose to discover approximate primary functional dependency (aPFD) for web tables, which focus on the determination relationship between primary attributes and non-primary attributes and are more helpful for entity column detection and topic discovery on web tables. Based on association rules and information theory, we propose metrics Conf and InfoGain to evaluate PFDs. By quantifying PFDs' strength and designing pruning strategies to eliminate false positives, our method could select minimal non-trivial approximate PFD effectively and are scalable to large tables. The comprehensive experimental results on real web datasets show that our method significantly outperforms previous work in both effectiveness and efficiency.

This work proposes a design methodology that saves the power dissipation under voltage over-scaling (VOS) operation. The key idea of the proposed design methodology is to combine critical path isolation (CPI) and bit-width scaling (BWS) under the constraint of computational quality, e.g., Peak Signal-to-Noise Ratio (PSNR) in the image processing domain. Conventional CPI inherently cannot reduce the delay of intrinsic critical paths (CPs), which may significantly restrict the power saving effect. On the other hand, the proposed methodology tries to reduce both intrinsic and non-intrinsic CPs. Therefore, our design dramatically reduces the supply voltage and power dissipation while satisfying the quality constraint. Moreover, for reducing co-design exploration space, the proposed methodology utilizes the exclusiveness of the paths targeted by CPI and BWS, where CPI aims at reducing the minimum supply voltage of non-intrinsic CP, and BWS focuses on intrinsic CPs in arithmetic units. From this key exclusiveness, the proposed design splits the simultaneous optimization problem into three sub-problems; (1) the determination of bit-width reduction, (2) the timing optimization for non-intrinsic CPs, and (3) investigating the minimum supply voltage of the BWS and CPI-applied circuit under quality constraint, for reducing power dissipation. Thanks to the problem splitting, the proposed methodology can efficiently find quality-constrained minimum-power design. Evaluation results show that CPI and BWS are highly compatible, and they significantly enhance the efficacy of VOS. In a case study of a GPGPU processor, the proposed design saves the power dissipation by 42.7% with an image processing workload and by 51.2% with a neural network inference workload.

Powerful jammers are able to disable consumer-grade global navigation satellite system (GNSS) receivers under normal operating conditions. Conventional anti-jamming techniques based on the time-domain are unable to effectively suppress wide-band interference, such as chirp-like jammer. This paper proposes a novel anti-jamming architecture, combining wavelet packet signal analysis with adaptive filtering theory to mitigate chirp interference. Exploiting the excellent time-frequency resolution of wavelet technologies makes it possible to generate a reference chirp signal, which is basically a “de-noised” jamming signal. The reference jamming signal then is fed into an adaptive predictor to function as a refined jamming signal such that it predicts a replica of the jammer from the received signal. The refined chirp signal is then subtracted from the received signal to realize the aim of anti-jamming. Simulation results demonstrate the effectiveness of the proposed method in combating chirp interference in Galileo receivers. We achieved jamming-to-signal power ratio (JSR) of 50dB with an acquisition probability exceeding 90%, which is superior to many anti-jamming techniques based on the time-domain, such as conventional adaptive notch filters. The proposed method was also implemented in an software-defined GPS receiver for further validation.

Saliency detection for videos has been paid great attention and extensively studied in recent years. However, various visual scene with complicated motions leads to noticeable background noise and non-uniformly highlighting the foreground objects. In this paper, we proposed a video saliency detection model using spatio-temporal cues. In spatial domain, the location of foreground region is utilized as spatial cue to constrain the accumulation of contrast for background regions. In temporal domain, the spatial distribution of motion-similar regions is adopted as temporal cue to further suppress the background noise. Moreover, a backward matching based temporal prediction method is developed to adjust the temporal saliency according to its corresponding prediction from the previous frame, thus enforcing the consistency along time axis. The performance evaluation on several popular benchmark data sets validates that our approach outperforms existing state-of-the-arts.

Soft errors caused by energetic particle strikes in on-chip cache memories have become a critical challenge for microprocessor design. Architectural vulnerability factor (AVF), which is defined as the probability that a transient fault in the structure would result in a visible error in the final output of a program, has been widely employed for accurate soft error rate estimation. Recent studies have found that designing soft error protection techniques with the awareness of AVF is greatly helpful to achieve a tradeoff between performance and reliability for several structures (i.e., issue queue, reorder buffer). Considering large on-chip L2 cache, redundancy-based protection techniques (such as ECC) have been widely employed for L2 cache data integrity with high costs. Protecting caches without accurate knowledge of the vulnerability characteristics may lead to the over-protection, thus incurring high overheads. Therefore, designing AVF-aware protection techniques would be attractive for designers to achieve a cost-efficient protection for caches, especially at early design stage. In this paper, we propose an improved AVF estimation framework for conducing comprehensive characterization of dynamic behavior and predictability of L2 cache vulnerability. We propose to employ Bayesian Additive Regression Trees (BART) method to accurately model the variation of L2 cache AVF and to quantitatively explain the important effects of several key performance metrics on L2 cache AVF. Then we employ bump hunting technique to extract some simple selecting rules based on several key performance metrics for a simplified and fast estimation of L2 cache AVF. Using the simplified L2 cache AVF estimator, we develop an AVF-aware ECC technique as an example to demonstrate the cost-efficient advantages of the AVF prediction based dynamic fault tolerant techniques. Experimental results show that compared with traditional full ECC technique, AVF-aware ECC technique reduces the L2 cache access latency by 16.5% and saves power consumption by 11.4% for SPEC2K benchmarks averagely.

By using electric-field-induced optical second-harmonic generation (EFISHG) measurement, we investigated interfacial carrier behavior in organic solar cells (OSCs) with a blocking layer of bathocuproine (BCP). Results evidently showed that the Maxwell-Wagner type excess charges accumulate on both pentacene/C60 and C60/BCP interfaces. Also, the measurement under short-circuit and open-circuit conditions clearly showed the different photo-induced carrier behaviors in the OSCs devices. Our work proved that the dielectric nature of OSCs dominates the operation of our OSCs and the EFISHG technique is very effective to characterize the dielectric performance of the OSCs.

There has been increasing demand to research the measuring method to characterize the batch consistency of contact rivets. An automated test equipment has been described that makes it possible to measure the electrical contact resistance with high efficiency. The relationship between contact force and contact resistance during the loading and unloading process was measured explicitly using AgPd alloy, stainless steel and sapphire substrate material with Au coatings as sphere indenters separately. To explain the phenomena of contact resistance decreasing more slowly than the traditional theoretical results during loading, the indenter with coating and rivet are modeled by using the commercial FEM software COMSOL Multiphysics. Besides the constriction resistance, the transition region Au coating resistance and the bulk resistance of the substrate are deduced from the simulated current lines profiles and iso-potentials. The difference of electrical conductivity between indenter material and gold coating is the reason for the occurrence of the transition region.