Conventional orthogonal frequency division multiplexing (OFDM) system utilizes cyclic prefix (CP) to remove the channel-induced inter-symbol interference (ISI) at the cost of lower spectral efficiency. In this paper, a generalized sidelobe canceller (GSC) based equalizer for ISI suppression is proposed for uplink multi-antenna OFDM systems without CP. Based on the block representation of the CP-free OFDM system, there is a natural formulation of the ISI suppression problem under the GSC framework. By further exploiting the signal and ISI signature matrix structures, a computationally efficient partially adaptive (PA) implementation of the GSC-based equalizer is proposed for complexity reduction. The proposed scheme can be extended for the design of a pre-equalizer, which pre-suppresses the ISI and realizes CP-free downlink transmission to ease the computational burden of the mobile unit (MU). Simulation results show that the proposed GSC-based solutions yield equalization performances almost identical to that obtained by the conventional CP-based OFDM systems and are highly resistant to the increase in channel delay spread.

The wavelet transform (WT) has recently emerged as a powerful tool for image compression. In this paper, a new image compression technique combining the genetic algorithm (GA) and grey-based competitive learning network (GCLN) in the wavelet transform domain is proposed. In the GCLN, the grey theory is applied to a two-layer modified competitive learning network in order to generate optimal solution for VQ. In accordance with the degree of similarity measure between training vectors and codevectors, the grey relational analysis is used to measure the relationship degree among them. The GA is used in an attempt to optimize a specified objective function related to vector quantizer design. The physical processes of competition, selection and reproduction operating in populations are adopted in combination with GCLN to produce a superior genetic grey-based competitive learning network (GGCLN) for codebook design in image compression. The experimental results show that a promising codebook can be obtained using the proposed GGCLN and GGCLN with wavelet decomposition.

Emerging video surveillance technologies are based on foreground detection to achieve event detection automatically. Integration foreground detection with a modern multi-camera surveillance system can significantly increase the surveillance efficiency. The foreground detection often leads to high computational load and increases the cost of surveillance system when a mass deployment of end cameras is needed. This paper proposes a DSP-based foreground detection algorithm. Our algorithm incorporates a temporal data correlation predictor (TDCP) which can exhibit the correlation of data and reduce computation based on this correlation. With the DSP-oriented foreground detection, an adaptive frame rate control is developed as a low cost solution for multi-camera surveillance system. The adaptive frame rate control automatically detects the computational load of foreground detection on multiple video sources and adaptively tunes the TDCP to meet the real-time specification. Therefore, no additional hardware cost is required when the number of deployed cameras is increased. Our method has been validated on a demonstration platform. Performance can achieve real-time CIF frame processing for a 16-camera surveillance system by single-DSP chip. Quantitative evaluation demonstrates that our solution provides satisfied detection rate, while significantly reducing the hardware cost.

Traditional face swapping technologies require that the faces of source images and target images have similar pose and appearance (usually frontal). For overcoming this limit in applications this paper presents a pose-free face swapping method based on personalized 3D face modeling. By using a deformable 3D shape morphable model, a photo-realistic 3D face is reconstructed from a single frontal view image. With the aid of the generated 3D face, a virtual source image of the person with the same pose as the target face can be rendered, which is used as a source image for face swapping. To solve the problem of illumination difference between the target face and the source face, a color transfer merging method is proposed. It outperforms the original color transfer method in dealing with the illumination gap problem. An experiment shows that the proposed face reconstruction method is fast and efficient. In addition, we have conducted experiments of face swapping in a variety of scenarios such as children's story book, role play, and face de-identification stripping facial information used for identification, and promising results have been obtained.

With the development of network technology, next-generation networks must satisfy many new requirements for network functions and performance. The processing of overlong packet fields is one of the requirements and is also the basis for ID-based routing and content lookup, and packet field addition/deletion mechanisms. The current SDN switches do not provide good support for the processing of overlong fields. In this paper, we propose a series of optimization mechanisms for protocol-oblivious instructions, in which we address the problem of insufficient support for overlong data in existing SDN switches by extending the bit width of instructions and accelerating them using SIMD instruction sets. We also provide an intermediate representation of the protocol-oblivious instruction set to improve the efficiency of storing and reading instruction blocks, and further reduce the execution time of instruction blocks by preprocessing them. The experiments show that our approach improves the performance of overlong data processing by 56%. For instructions involving packet field addition and deletion, the improvement in performance reaches 455%. In normal forwarding scenarios, our solution reduces the packet forwarding latency by around 30%.

In this paper, we present CB-Power, a hierarchical power analysis and characterization environment of cell-based CMOS circuits. The environment includes two parts, a cell characterization system for timing, input capacitance as well as power and a cell-based power estimation system. The characterization system can characterize basic, complex and transmission gates. During the characterization, input slew rate, output loading, capacitive feedthrough effect and the logic state dependence of nodes in a cell are all taken into account. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power and dynamic power. With the characterization data, a cell-based power estimator (CBPE) embedded in Verilog-XL is used for estimating the power consumption of the gates in a circuit. CBPE is also a hierarchical power estimator. Macrocells such as flip-flops and adders are partitioned into primitive gates during power estimation. Experimental results on a set of MCNC benchmark circuits show that the power estimation based on our power modeling and characterization provides within 6% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.

As the function of a system getting more complex, IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.

This paper introduces a texture analysis mechanism utilizing multiresolution technique to reduce false motion detection and hence thoroughly improve the interpolation results for high-quality deinterlacing. Conventional motion-adaptive deinterlacing algorithm selects from inter-field and intra-field interpolations according to motion. Accurate determination of motion information is essential for this purpose. Fine textures, having high local pixel variation, tend to cause false detection of motion. Based on hierarchical wavelet analysis, this algorithm provides much better perceptual visual quality and considerably higher PSNR than other motion adaptive deinterlacers as shown. In addition, a recursive 3-field motion detection algorithm is also proposed to achieve better performance than the traditional 2-field motion detection algorithm with little memory overhead.

There are a great amount of various resources described in many different ways for service oriented grid environment, while traditional grid resource discovery methods could not fit more complex future grid system. Therefore, this paper proposes a novel grid resource discovery method based on association rule hypergraph partitioning algorithm which analyzes user behavior in history transaction records to provide personality service for user. And this resource discovery method gives a new way to improve resource retrieval and management in grid research.

In this paper, the application of an unsupervised parallel approach called the Fuzzy Hopfield Neural Network (FHNN) for vector qunatization in image compression is proposed. The main purpose is to embed fuzzy reasoning strategy into neural networks so that on-line learning and parallel implementation for codebook design are feasible. The object is to cast a clustering problem as a minimization process where the criterion for the optimum vector qunatization is chosen as the minimization of the average distortion between training vectors. In order to generate feasible results, a fuzzy reasoning strategy is included in the Hopfield neural network to eliminate the need of finding weighting factors in the energy function that is formulated and based on a basic concept commonly used in pattern classification, called the "within-class scatter matrix" principle. The suggested fuzzy reasoning strategy has been proven to allow the network to learn more effectively than the conventional Hopfield neural network. The FHNN based on the within-class scatter matrix shows the promising results in comparison with the c-means and fuzzy c-means algorithms.