The rapid growth of IT technology has enabled ship navigation and automation systems to gain better functionality and safety. However, they generally have their own proprietary structures and networks, which makes interfacing with and remote access to them difficult. In this paper, we propose a total ship service framework that includes a ship area network to integrate separate system networks with heterogeneity and dynamicity, and a ship-shore communication infrastructure to support a remote monitoring and maintenance service using satellite communications. Finally, we present some ship service systems to demonstrate the applicability of the proposed framework.

We proposed a new motion vector (MV) smoothing using fuzzy weighting and vector median filtering for frame rate up-conversion. A fuzzy reasoning system adjusts the weighting values based on the local characteristics of MV field including block difference and block boundary distortion. The fuzzy weighting removes the affect of outliers and irregular MVs from the MV smoothing process. The simulation results show that the proposed algorithm can efficiently correct wrong MVs and thus improve visual quality of the interpolated frames better than conventional methods.

Higher frame-rates are essential in achieving more realistic representations. Since increasing the frame-rate increases the total amount of information, efficient coding methods are required. However, the statistical properties of such data, needed for designing sufficiently powerful encoders, have not been clarified. Conventional studies on encoding high frame-rate sequences do not consider the effect on the encoding bit-rate of the motion blur generated by the shutter being open. When the open interval of the shutter in the image pickup apparatus increases, motion blur occurs, which is known as the integral phenomenon. The integral phenomenon changes the statistical properties of the video signal. This paper derives, for high frame-rate video, a mathematical model that quantifies the relationship between frame-rate and bit-rate; it incorporates the effect of the low-pass filtering induced by the open shutter. A coding experiment confirms the validity of the mathematical model.

This paper reports the effect of corpus size on case frame acquisition for predicate-argument structure analysis in Japanese. For this study, we collect a Japanese corpus consisting of up to 100 billion words, and construct case frames from corpora of six different sizes. Then, we apply these case frames to syntactic and case structure analysis, and zero anaphora resolution, in order to investigate the relationship between the corpus size for case frame acquisition and the performance of predicate-argument structure analysis. We obtained better analyses by using case frames constructed from larger corpora; the performance was not saturated even with a corpus size of 100 billion words.

System implementation for e-Government initiatives should be reliable. Unreliable system implementation could, on the one hand, be insufficient to fulfill basic system requirements, and more seriously on the other hand, break the trust of citizens on governments. The objective of this paper is to advocate the use of formal methods in general, the OTS/CafeOBJ method in particular in this paper, to help develop reliable system implementation for e-Government initiatives. An experiment with the OTS/CafeOBJ method on an e-Government messaging framework proposed for providing citizens with seamless public services is described to back up our advocation. Two previously not well-clarified problems of the framework and their potential harm realized in this experiment are reported, and possible ways of revisions to the framework are suggested as well. The revisions are proved to be sufficient for making the framework satisfy certain desired properties.

Networking technologies have recently been evolving and network applications are now expected to support flexible composition of upper-layer network services, such as security, QoS, or personal firewall. We propose a multi-platform framework called FreeNA* that extends existing applications by incorporating the services based on user definitions. This extension does not require users to modify their systems at all. Therefore, FreeNA is valuable for experimental system usage. We implemented FreeNA on both Linux and Microsoft Windows operating systems, and evaluated their functionality and performance. In this paper, we describe the design and implementation of FreeNA including details on how to insert network services into existing applications and how to create services in a multi-platform environment. We also give an example implementation of a service with SSL, a functionality comparison with relevant systems, and our performance evaluation results. The results show that FreeNA offers finer configurability, composability, and usability than other similar systems. We also show that the throughput degradation of transparent service insertion is 2% at most compared with a method of directly inserting such services into applications.

In this paper, a new video frame interpolation method based on image morphing for frame rate up-conversion is proposed. In this method, image features are extracted by Scale-Invariant Feature Transform in each frame, and their correspondence in two contiguous frames is then computed separately in foreground and background regions. By using the above two functions, the proposed method accurately generates interpolation frames and thus achieves frame rate up-conversion.

It has been proved that wireless network coding can increase the throughput of multi-access system [2] and bi-directional system [5] by taking the advantage of the broadcast nature of electromagnetic waves. In this paper, we introduce the wireless network coding to cooperative multicast system. We establish a basic 2-source and 2-destination cooperative system model with arbitrary number of relays (2-N-2 system). Then two regenerative network coding (RNC) protocols are designed to execute the basic idea of network coding in complex field (RCNC) and Galois field (RGNC) respectively. We illuminate how network coding can enhance the throughput distinctly in cooperative multicast system. Power allocation schemes as well as precoder design are also carefully studied to improve the system performance in terms of system frame error probability (SFEP).

Cognitive Radio (CR) is expected to bring about a more flexible wireless communication environment by the efficient utilization of spectrum resources. In this paper, a CR coexisting with IEEE 802.11 Wireless Local Area Networks (WLANs) is proposed. In the Distributed Coordination Function (DCF) access scheme in IEEE 802.11 WLAN, a station (STA) transmits a data frame by executing a random backoff procedure after Distributed Inter Frame Space (DIFS) period, and the destination STA of the data frame responds with Ack frame to the source STA after Short Inter Frame Space (SIFS) period. After the Ack frame is transmitted, the same procedures are repeated. The proposed CR terminal recognizes the DIFS period and the SIFS period, and then it transmits CR signals during these periods with the transmission power that does not affect the IEEE 802.11 WLAN protocol. Thus, the proposed CR terminals recognize the periods during which IEEE 802.11 STAs do not transmit any frames and they use the periods to transmit CR signals. In this paper, IEEE 802.11 WLAN STA that has the capability for the proposed CR technique in addition to the normal 802.11 WLAN capability is considered and the improved average throughputs by the CR communications are evaluated in the computer simulation, and then the effectiveness of the proposed method is clarified.

In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, the circuit performance such as the clock period is expected to be improved by delay insertion. However, if the amount of inserted delays is too much, then the circuit is changed too much and the circuit performance might not be improved. In this paper, we propose an efficient delay insertion method that minimizes the amount of inserted delays in the clock period improvement in general-synchronous framework. In the proposed method, the amount of inserted delays is minimized by using an appropriate clock schedule and by inserting delays into appropriate places in the circuit. Experiments show that the proposed method can obtain optimum solutions in short time in many cases.

In RFID systems, collision resolution is a significant issue in fast tag identification. This letter presents a dynamic frame-slotted ALOHA algorithm that uses a collision factor (DFSA-CF). This method enables fast tag identification by estimating the next frame size with the collision factor in the current frame. Simulation results show that the proposed method reduces slot times Required for RFID identification. When the number of tags is larger than the frame size, the efficiency of the proposed method is greater than those of conventional algorithms.

The reduction of the peak power consumption of LSI is required to reduce the instability of gate operation, the delay increase, the noise, and etc. It is possible to reduce the peak power consumption by clock scheduling because it controls the switching timings of registers and combinational logic elements. In this paper, we propose a fast peak power wave estimation method for clock scheduling and fast clock scheduling methods for the peak power reduction. In experiments, it is shown that the peak power wave estimated by the proposed method in a few seconds is highly correlated with the peak power wave obtained by HSPICE simulation in several days. By using the proposed peak power wave estimation method, proposed clock scheduling methods find clock schedules that greatly reduce the peak power consumption in a few minutes.

Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior and topology. However, if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a gate-level register relocation method that reduces the number of registers while keeping the target clock period. In experiments, the proposed method reduces the number of registers in the practical time in most circuits.

The key to high performance in video coding lies on efficiently reducing the temporal redundancies. For this purpose, H.264/AVC coding standard has adopted variable block size motion estimation on multiple reference frames to improve the coding gain. However, the computational complexity of motion estimation is also increased in proportion to the product of the reference frame number and the intermode number. The mathematical analysis in this paper reveals that the prediction errors mainly depend on the image edge gradient amplitude and quantization parameter. Consequently, this paper proposes the image content based early termination algorithm, which outperforms the original method adopted by JVT reference software, especially at high and moderate bit rates. In light of rate-distortion theory, this paper also relates the homogeneity of image to the quantization parameter. For the homogenous block, its search computation for futile reference frames and intermodes can be efficiently discarded. Therefore, the computation saving performance increases with the value of quantization parameter. These content based fast algorithms were integrated with Unsymmetrical-cross Multihexagon-grid Search (UMHexagonS) algorithm to demonstrate their performance. Compared to the original UMHexagonS fast matching algorithm, 26.14-54.97% search time can be saved with an average of 0.0369 dB coding quality degradation.

In this paper, we present a reconfigurable processor infrastructure to accelerate Java applications, called Jaguar. The Jaguar infrastructure consists of a compiler framework and a runtime environment support. The compiler framework selects a group of Java methods to be translated into hardware for delivering the best performance under limited resources, and translates the selected Java methods into Verilog synthesizable code modules. The runtime environment support includes the Java virtual machine (JVM) running on a host processor to provide Java execution environment to the generated Java accelerator through communication interface units while preserving Java semantics. Our compiler infrastructure is a tightly integrated and solid compiler-aided solution for Java reconfigurable computing. There is no limitation in generating synthesizable Verilog modules from any Java application while preserving Java semantics. In terms of performance, our infrastructure achieves the speedup by 5.4 times on average and by up to 9.4 times in measured benchmarks with respect to JVM-only execution. Furthermore, two optimization schemes such as an instruction folding and a live buffer removal can reduce 24% on average and up to 39% of the resource consumption.

Compared with previous standards, H.264/AVC adopts variable block size motion estimation (VBSME) and multiple reference frames (MRF) to improve the video quality. Full search motion estimation algorithm (FS), which calculates every search candidate in the search window for 7 block type with multiple reference frames, consumes massive computation power. Mathematical analysis reveals that the aliasing problem of subsampling algorithm comes from high frequency signal components. Moreover, high frequency signal components are also the main issues that make MRF algorithm essential. As we know, a picture being rich of texture must contain lots of high frequency signals. So based on these mathematical investigations, two fast VBSME algorithms are proposed in this paper, namely edge block detection based subsampling method and motion vector based MRF early termination algorithm. Experiments show that strong correlation exists among the motion vectors of those blocks belonging to the same macroblock. Through exploiting this feature, a dynamically adjustment of the search ranges of integer motion estimation is proposed in this paper. Combing our proposed algorithms with UMHS almost saves 96-98% Integer Motion Estimation (IME) time compared to the exhaustive search algorithm. The induced coding quality loss is less than 0.8% bitrate increase or 0.04 dB PSNR decline on average.

Wyner and Ziv characterized the rate distortion function for lossy source coding with side information at the decoder. It is well known that for the quadratic Gaussian case, the Wyner-Ziv rate-distortion function coincides with the conditional rate-distortion function. In this paper, we extend the problem to the coding of multivariate Gaussian source with multiple Gaussian side information at the decoder. The achievable region is obtained, and it is easily extended to the case that the difference between the source and the side information is multivariate Gaussian, no matter what distributions the source and the side information are. We apply this theoretical model to Distributed Video Coding (DVC) by considering the difference of the Distributed frame (D frame) and the Side-information frame (S frame) to be multivariate Gaussian distributed. This introduces rate allocation problem into DVC, which can be solved by a reverse water-filling method. Simulation results show that around 1.5-2 dB coding gain benefits from the multivariate Gaussian Wyner-Ziv coding model.

UHF radio frequency identification (RFID) has gathered significant interest in the field of long-distance automatic identification applications. Since UHF RFID shares the frequency band with other RFID and/or other wireless systems, it is important to determine how much interference can be applied without causing a significant degradation of anti-collision speed. In this paper, the permissible link quality for RFID anti-collision in a practical environment is discussed by considering an erroneous communication link, taking into account of bit encoding and the type of interference. We approach the quantification of permissible link quality experimentally along with protocol simulations and the mathematical analyses. An international standard protocol, employing frame slotted ALOHA, was used as the air protocol. For these investigations, the present authors developed a protocol simulator. The simulation results were compared with analytical values based on Poisson distribution. The investigation in the return (tag to reader) link, and the forward (reader to tag) link, were analyzed separately. As result of the protocol simulation, it is generally important to secure the Pulse Error Rate 10-4 or better in both return and forward links for the anti-collision of 64 or less tags. The quality of the return link may be relaxed when the application does not require fast anti-collision. The degradation of the forward link, on the other hand, may entail loss of important commands, resulting in extremely slow anti-collision. It is measured experimentally that the required link quality can be relaxed by up to 10 dB in the return links and by 5 dB in the forward link when the primary source of interference originates in the interfering readers.

Motion-compensated frame interpolation (MCFI) is widely used to smoothly display low frame rate video sequences by synthesizing and inserting new frames between existing frames. The temporal shift interpolation technique (TSIT) is popular for frame interpolation of video sequences that are encoded by a block-based video coding standard such as MPEG-4 or H.264/AVC. TSIT assumes the existence of a motion vector (MV) and may not result in high-quality interpolation for intra-mode blocks that do not have MVs. This paper proposes a new frame interpolation algorithm mainly designed for intra-mode blocks. In order to improve the accuracy of pixel interpolation, the new algorithm proposes sub-pixel interpolation and the reuse of MVs for their refinement. In addition, the new algorithm employs two different interpolation modes for inter-mode blocks and intra-mode blocks, respectively. The use of the two modes reduces ghost artifacts but potentially increases blocking effects between the blocks interpolated by different modes. To reduce blocking effects, the proposed algorithm searches the boundary of an object and interpolates all blocks in the object in the same mode. Simulation results show that the proposed algorithm improves PSNR by an average of 0.71 dB compared with the TSIT with MV refinement and also significantly improves the subjective quality of pictures by reducing ghost artifacts.

This paper proposes a self-test method of coarse grain dynamically reconfigurable processors (DRPs) without hardware overhead. In the method, processor elements (PEs) compose a test frame, which consists of test pattern generators (TPGs), processor elements under test (PEUTs) and response analyzers (RAs), while testing themselves one another by changing test frames appropriately. We design several test frames with different structures, and discuss the relationship of the structures to the numbers of contexts and test frames for testing all the functions of PEs. A case study shows that there exists an optimal test frame which minimizes the test application time under a constraint.