This paper analyzes the effect of error propagation of decision feedback equalizer (DFE) for PAM4 based 400Gb/s Ethernet. First, an analytic model for the error propagation is proposed to estimate the probability of different burst error length due to error propagation for PAM4 link system with multi-tap TX FFE (Feed Forward Equalizer) + RX DFE architecture. After calculating the symbol error rate (SER) and bit error rate (BER) based on the probability model, the theoretical analysis about the impact of different equalizer configurations on BER is compared with the simulation results, and then BER performance with FEC (Forward Error Correction) is analyzed to evaluate the effect of DFE error propagation on PAM4 link. Finally, two FEC interleaving schemes, symbol and bit interleaving, are employed in order to reduce BER further and then the theoretical analysis and the simulation result of their performance improvement are also evaluated. Simulation results show that at most 0.52dB interleaving gain can be achieved compared with non-interleaving scheme just at a little cost in storing memory and latency. And between the two interleaving methods, symbol interleaving performs better compared with the other one from the view of tradeoff between the interleaving gain and the cost and can be applied for 400Gb/s Ethernet.

We review recent progress in integrated photonics devices and their applications for datacom. In addition to current technology used in 100-Gigabit Ethernet (100GbE) with a compact form-factor of the transceiver, the next generation of technology for 400GbE seeks a larger number of wavelengths with a more sophisticated modulation format and higher bit rate per wavelength. For wavelength scalability and functionality, planar lightwave circuits (PLCs), such as arrayed waveguide gratings (AWGs), will be important, as well higher-order-modulation to ramp up the total bit rate per wavelength. We introduce integration technology for a 100GbE optical sub-assembly that has a 4λ x 25-Gb/s non-return-to-zero (NRZ) modulation format. For beyond 100GbE, we also discuss applications of 100GbE sub-assemblies that provide 400-Gb/s throughput with 16λ x 25-Gb/s NRZ and bidirectional 8λ x 50-Gb/s four-level pulse amplitude modulation (PAM4) using PLC cyclic AWGs.