As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper presents an efficient reverse calculation method to lower the power consumption by reducing the number of memory accesses required in turbo decoding. The reverse calculation method is proposed for the Max-log-MAP algorithm, and it is combined with a scaling technique to achieve a new decoding algorithm, called hybrid log-MAP, that results in a similar BER performance to the log-MAP algorithm. For the W-CDMA standard, experimental results show that 80% of memory accesses are reduced through the proposed reverse calculation method. A hybrid log-MAP turbo decoder based on the proposed reverse calculation reduces power consumption and memory size by 34.4% and 39.2%, respectively.

Thanks to the possibility of being able to implement them in decoders in relatively simple ways, turbo codes are being applied to various areas of engineering. Wireless communications is one of the most important applications, where various types of data communications are required and the speed of information and data capacity need to be changed with different rates of parity bit puncturing being adopted to obtain highly efficient transmission. In such applications, adaptation to various turbo-coding specifications on a real-time basis is needed as well as good bit-error-rate performance. We present a new concept for simplifying metric computation and programmable circuit configurations that focuses on the convolutional decoder, which occupies a significant portion of allocated hardware, and we fundamentally treat a simplified log-domain version of the maximum a posteriori (MAP) algorithm, usually know as the Max-Log-MAP (MLM), as a base algorithm. The sliding window method provides an attractive way of computing metric values for the Max-Log-MAP. However, this algorithm does cause degradation, especially when a high rate code is used, generated by bit puncturing. We propose a new means of avoiding this problem and demonstrate that the sliding window, and a modified version as well as other methods, should be flexibly selected to utilize hardware resources depending on turbo specifications. We demonstrated that our proposed methods provide almost the same BER performance as MLM even when a high rate puncturing rate of 5/6 is applied. Finally, we describe the new hardware architecture that we invented to cope with these programmability issues. We show that a turbo-decoding circuit can be implemented in the processor core and its associated unit to configure an LSI macro circuit. The proposed unit has about 60-K gates. We demonstrate that this architecture can be applied to about the 1.5-Mbps information bit throughput of turbo decoding with a 200-MHz clock cycle, which is achievable with today's advanced CMOS technologies.

Turbo coding is a powerful coding technique that can provide highly reliable data transmission at extremely low signal-to-noise ratios. Owing to the computational complexity of the employed decoding algorithm, the realization of turbo decoders usually takes a large amount of memory space and potentially long decoding delay. Therefore, an efficient memory management strategy becomes one of the key factors toward successfully implementing turbo decoders. This paper focuses on the development of general structures for efficient memory management of turbo decoders employing the sliding-window (Log-) MAP algorithm. Three different structures and the associated mathematic representations are derived to evaluate the required memory size, average decoding rate, and latency based on the speed and the number of the adopted processors. Comparative results show the dependency of the resulting performance based on a set of parameters; thus provide useful and general information on practical implementations of turbo decoders.

Several implementation methods for a MAP decoder are proposed in this paper. Using a novel pipeline structured time-shared process, the authors are able to efficiently overcome the restrictions imposed by the recursion process on state metrics, and the complexity of the MAP decoder can be reduced to a level on the order of a SOVA (Soft Output Viterbi Algorithm) decoder. In addition, the authors propose an efficient controller structure that can be used for variable frame-size systems such as cdma-2000. The MAP decoder using a block-wise algorithm designed here was implemented in only one 20,000 gate circuit. It was validated by VHDL, which was compared with the results of the initial simulation (C programs). The decoder demonstrated a 300 kbps decoding processing ability with 8 iterations on a FPGA circuit, with a deviation only about 0.1-0.2 dB greater than that for an ideal MAP decoder, even when all hardware environments are considered.

In this paper, we consider the applicability of turbo code for future third generation (3G) mobile telecommunication systems. Futhermore, we propose a simple method of estimating the channel variance which is necessary for the MAP (Maximum A Posteriori) decoding algorithm. We compare the performance of turbo code with a known channel variance, conventional variance estimate and variance estimated by our proposed technique. We show that our variance estimation scheme is adequate for 3G WB-CDMA mobile systems without degradation of turbo code performance.

Turbo codes have fascinated many coding researchers because of thier near-Shannon-limit error correction performance. In this paper, we discuss multi-dimensional turbo codes which are parallel concatenation of multiple constituent codes. The average upper bound to bit error probability of multidimensional turbo codes is derived. The bound shows that the interleaver gains of this kind of codes are larger than that of conventional two-dimensional turbo codes. Simplified structures of multi-dimensional turbo encoder and decoder are proposed for easier implementation. Simulation results show that for a given interleaver size, by increasing the dimension, great performance improvement can be obtained.

This paper presents a novel approach to a soft-output equalizer, which makes a symbol-by-symbol soft-decision based on a posteriori probabilities (APP's) criterion in the presence of intersymbol interference. The authors propose a soft-output Viterbi equalizer (SOVE) employing expanded memory length in a trellis of the Viterbi algorithm with small arithmetic complexity. The proposed equalizer gives suboptimum soft-decision closer to that of a equalizer with the maximum a posteriori probabilities (MAP) algorithm than the conventional SOVE.