We fabricated metal-oxide-semiconductor (MOS) devices with Pt/Ta2O5 gate stacks and investigated their electrical and structural properties. As increasing RF magnetron sputter-deposition time of Ta2O5 film, the values of equivalent oxide thickness (EOT) and flat band voltage (VFB) increase whilst the density of interfacial trap (Dit) gradually decreases. The effective metal work function (Φm,eff) of Pt metal gate, extracted from the relations of EOT versus VFB are calculated to be ∼5.29 eV, implying that Fermi-level pinning in Ta2O5 gate dielectric is insignificant.

In this study, the microwave dielectric properties of the Mg4Ta2O9 and Mg5Ta4O15 ceramics with composition ratio and sintering temperature were investigated and the dielectric resonators with these ceramics were simulated. TiO2 was doped in the Mg4Ta2O9 ceramics for improvement of temperature property. The (1-x)Mg4Ta2O9-xTiO2 and Mg5Ta4O15 ceramics were prepared by solid-state reaction method. According to the X-ray diffraction data, the (1-x)Mg4Ta2O9-xTiO2 ceramics had main phase of the Mg4Ta2O9 and MgTi2O5 peaks were appeared by additions of TiO2. In the Mg5Ta4O15 ceramics, the Mg4Ta2O9 and MgTa2O6 phase were coexisted and Mg5Ta4O15 phase was appeared with increments of sintering temperature. Microwave dielectric properties of (1-x)Mg4Ta2O9-xTiO2 ceramics were affected by MgTi2O5 and TiO2 phase. The quality factor had a little decrement compared to pure Mg4Ta2O9, but there was excellent improvement in TCRF by addition of TiO2. Densifications of the Mg4Ta2O9 and MgTa2O6 and existence of the Mg5Ta4O15 phase had influence on the microwave dielectric properties of the Mg5Ta4O15 ceramics. Dielectric constant, quality factor and TCRF of the (1-x)Mg4Ta2O9-xTiO2 and Mg5Ta4O15 ceramics sintered at 1450 were 11.5622.5, 24980186410 GHz, -36.02+19.72 ppm/ and 8.2, 89473 GHz, -10.91 ppm/, respectively. ADS was used for simulation of DR. The simulated DR with the 0.5Mg4Ta2O9-0.5TiO2 and Mg5Ta4O15 ceramics had the S21 of -35.034 dB at 11.97 GHz and -28.493 dB at 10.50 GHz, respectively.

Material research on capacitor dielectrics for DRAM applications is reviewed. The state of the art technologies to prepare Si3N4,Ta2O5, and SrTiO3 thin films for capacitors are described. The down-scaling limits for Si3N4 and Ta2O5 capacitors seem to be 3.5 and 1.5 nm SiO2 equivalent thickness, respectively. Combined with a rugged polysilicon electrode surface,Si3N4 and Ta2O5 based-capacitors are available for 256 Mbit and 1 Gbit DRAMs. At the present time, the minimum SiO2 equivalent thickness for high permittivity materials is around 1 nm with the leakage current density of 10-7 A/cm2. Among the great variety of ferroelectrics, two families of materials,i.e., Pb (Zr, Ti) O3 and (Ba, Sr) TiO3 have emerged as the most promising candidates for 1 Gbit DRAMs and beyond. If the chemical vapor deposition technology can be established for these materials, capacitor dielectrics should not be a limiting issue for Gbit DRAMs.