The architecture and implementation of a novel processor suitable wireless terminal applications, is introduced. The wireless terminal is based on the novel dual-mode baseband processor for DECT and GSM, which supports both heterodyne and direct conversion terminal architectures and is capable to undertake all baseband signal processing, and an innovative direct conversion low power modulator/demodulator for DECT and GSM. The state of the art design methodologies for embedded applications and innovative low-power design steps followed for a single chip solution. The performance of the implemented dual mode direct conversion wireless terminal was tested and measured for compliance to the standards. The developed innovative terminal fulfils all the requirements and specifications imposed by the DECT and GSM standards.

A novel approach to the cache coherent Multistage Interconnection Network (MIN) called the MINC (MIN with Cache control mechanism) is proposed. In the MINC, the directory is located only on the shared memory using the Reduced Hierarchical Bit-map Directory schemes (RHBDs). In the RHBD, the bit-map directory is reduced and carried in the packet header for quick multicasting without accessing the directory in each hierarchy. In order to reduce unnecessary packets caused by compacting the bit map in the RHBD, a small cache called the pruning cache is introduced in the switching element. The simulation reveals the pruning cache works most effectively when it is provided in every switching element of the first stage, and it reduces the congestion more than 50% with only 4 entries. The MINC cache control chip with 16 inputs/outputs is implemented on the LPGA (Laser Programmable Gate Array), and works with a 66 MHz clock.

In this study, we propose a system of N Wien-bridge oscillators with the same natural frequency coupled by one resistor, and investigate synchronization phenomena in the proposed system. Because the structure of the system is different from that of LC oscillators systems proposed in our previous works, this system cannot exhibit N-phase oscillations but 3-phase and in-phase oscillations. Also in this system, we can get an extremely large number of steady phase states by changing the initial states. In particular, when N is not so large, we can get more phase states in this system than that of the LC oscillators systems. Because this system does not include any inductors and is strong against phase error this system is much more suitable for applications on VLSI compared with coupled system of van der Pol type LC oscillators.