IEICE TRANSACTIONS on Information
MINC: Multistage Interconnection Network with Cache Control Mechanism
Summary :
A novel approach to the cache coherent Multistage Interconnection Network (MIN) called the MINC (MIN with Cache control mechanism) is proposed. In the MINC, the directory is located only on the shared memory using the Reduced Hierarchical Bit-map Directory schemes (RHBDs). In the RHBD, the bit-map directory is reduced and carried in the packet header for quick multicasting without accessing the directory in each hierarchy. In order to reduce unnecessary packets caused by compacting the bit map in the RHBD, a small cache called the pruning cache is introduced in the switching element. The simulation reveals the pruning cache works most effectively when it is provided in every switching element of the first stage, and it reduces the congestion more than 50% with only 4 entries. The MINC cache control chip with 16 inputs/outputs is implemented on the LPGA (Laser Programmable Gate Array), and works with a 66 MHz clock.
- Publication
- IEICE TRANSACTIONS on Information Vol.E80-D No.9 pp.863-870
- Publication Date
- 1997/09/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
- Category
- Interconnection Networks
Authors
Keyword
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Toshihiro HANAWA, Takayuki KAMEI, Hideki YASUKAWA, Katsunobu NISHIMURA, Hideharu AMANO, "MINC: Multistage Interconnection Network with Cache Control Mechanism" in IEICE TRANSACTIONS on Information,
vol. E80-D, no. 9, pp. 863-870, September 1997, doi: .
Abstract: A novel approach to the cache coherent Multistage Interconnection Network (MIN) called the MINC (MIN with Cache control mechanism) is proposed. In the MINC, the directory is located only on the shared memory using the Reduced Hierarchical Bit-map Directory schemes (RHBDs). In the RHBD, the bit-map directory is reduced and carried in the packet header for quick multicasting without accessing the directory in each hierarchy. In order to reduce unnecessary packets caused by compacting the bit map in the RHBD, a small cache called the pruning cache is introduced in the switching element. The simulation reveals the pruning cache works most effectively when it is provided in every switching element of the first stage, and it reduces the congestion more than 50% with only 4 entries. The MINC cache control chip with 16 inputs/outputs is implemented on the LPGA (Laser Programmable Gate Array), and works with a 66 MHz clock.
URL: https://global.ieice.org/en_transactions/information/10.1587/e80-d_9_863/_p
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@ARTICLE{e80-d_9_863,
author={Toshihiro HANAWA, Takayuki KAMEI, Hideki YASUKAWA, Katsunobu NISHIMURA, Hideharu AMANO, },
journal={IEICE TRANSACTIONS on Information},
title={MINC: Multistage Interconnection Network with Cache Control Mechanism},
year={1997},
volume={E80-D},
number={9},
pages={863-870},
abstract={A novel approach to the cache coherent Multistage Interconnection Network (MIN) called the MINC (MIN with Cache control mechanism) is proposed. In the MINC, the directory is located only on the shared memory using the Reduced Hierarchical Bit-map Directory schemes (RHBDs). In the RHBD, the bit-map directory is reduced and carried in the packet header for quick multicasting without accessing the directory in each hierarchy. In order to reduce unnecessary packets caused by compacting the bit map in the RHBD, a small cache called the pruning cache is introduced in the switching element. The simulation reveals the pruning cache works most effectively when it is provided in every switching element of the first stage, and it reduces the congestion more than 50% with only 4 entries. The MINC cache control chip with 16 inputs/outputs is implemented on the LPGA (Laser Programmable Gate Array), and works with a 66 MHz clock.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - MINC: Multistage Interconnection Network with Cache Control Mechanism
T2 - IEICE TRANSACTIONS on Information
SP - 863
EP - 870
AU - Toshihiro HANAWA
AU - Takayuki KAMEI
AU - Hideki YASUKAWA
AU - Katsunobu NISHIMURA
AU - Hideharu AMANO
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E80-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 1997
AB - A novel approach to the cache coherent Multistage Interconnection Network (MIN) called the MINC (MIN with Cache control mechanism) is proposed. In the MINC, the directory is located only on the shared memory using the Reduced Hierarchical Bit-map Directory schemes (RHBDs). In the RHBD, the bit-map directory is reduced and carried in the packet header for quick multicasting without accessing the directory in each hierarchy. In order to reduce unnecessary packets caused by compacting the bit map in the RHBD, a small cache called the pruning cache is introduced in the switching element. The simulation reveals the pruning cache works most effectively when it is provided in every switching element of the first stage, and it reduces the congestion more than 50% with only 4 entries. The MINC cache control chip with 16 inputs/outputs is implemented on the LPGA (Laser Programmable Gate Array), and works with a 66 MHz clock.
ER -
English
