The evolution of VLSI chips towards larger die size, smaller feature size and faster clock speed makes the clock distribution an increasingly important issue. In this paper, we propose a new clock distribution network (CDN), namely Variant X-Tree, based on the idea of X-Architecture proposed recently for efficient wiring within VLSI chips. The Variant X-Tree CDN keeps the nice properties of equal-clock-path and symmetric structure of the typical H-Tree CDN, but results in both a lower maximal clock delay and a lower clock skew than its H-Tree counterpart, as verified by an extensive simulation study that incorporates simultaneously the effects of process variations and on-chip inductance. We also propose a closed-form statistical models for evaluating the skew and delay of the Variant X-Tree CDN. The comparison between the theoretical results and the simulation results indicates that the proposed statistical models can be used to efficiently and rapidly evaluate the performance of the variant X-Tree CDNs.

In this paper, we propose a new Interconnect Length Distribution (ILD) model to evaluate X architecture. X architecture uses 45-wire orientations in addition to 90-wire orientations, which contributes to reduce the total wire length and the number of vias. In this paper, we evaluated interconnect length distribution of diagonal (45orientations) and all-directional wiring. The average length and the longest length of interconnect are estimated, and 18% reduction in power consumption and 17% improvement in clock frequency can be obtained by the diagonal wiring in the experimental results. The all-directional wiring does not have large advantage as compared the diagonal wiring.