This paper is concerned with synthesizing VLSI array processors from iterative algorithms. Our primary objective is to obtain the highest processor efficiency but not the shortest completion time. Unlike most of the previous work that assumes the index space of the given iterative algorithm to be boundless, the proposed method takes into account the effects of the boundaries of the index space. Due to this consideration, the pseudo-dependence relations are excluded, and most of the independent computations can therefore be uniformly grouped. With the method described in this paper, the index space is partitioned into equal-size blocks and the corresponding computations are systematically and uniformly mapped into processing elements. The synthesized VLSI array processors possess the attractive feature of very high processor efficiency, which, in general, is superior to what is derived from the conventional linear transformation methods.

In this paper, we study the following node-to-node fault tolerant routing problem: In the presence of up to n-1 faulty nodes, find a fault-free path which connects any two non-faulty nodes s and t in an n-connected graph. For node-to-node fault tolerant routing in n-dimensional hypercubes Hn, we give an algorithm which finds a fault-free path s t of length at most in O(n) time, where d(s, t) is the distance between s and t. We also show that a fault-free path s t in Hn of length at most d(s, t)2i, 1i, can be found in time. For node-to-node fault tolerant routing in n-dimensional star graphs Gn, we give an algorithm which finds a fault-free path s t of length at most min{d(Gn)3, d(s, t)6} in O(n) time, where is the diameter of Gn. It is previously known that, in Hn, a fault-free path s t of length at most d(s, t) for d(s, t)n and at most d(s, t)2 for d(s, t)n can be found in O(d(s, t)n) time, and in Gn, a fault-free path s t of length at most min{d(Gn)1, d(s, t)4}can be found in O(d(s, t)n) time. When the time efficiency of finding the routing path is more important than the length of the path, the algorithms in this paper are better than the previous ones.

This paper establishes a general relation between the two-dimensional Least Mean Square (2-D LMS) algorithm and 2-D discrete orthogonal transforms. It is shown that the 2-D LMS algorithm can be used to compute the forward as well as the inverse 2-D orthogonal transforms in general for any input by suitable choice of the adaptation speed. Simulations are presented to verify the general relationship results.

This paper condiders a problem of logecal configuration in reconfigurable VCDN (Virtual Circuit Data Networks) which is analyzed through a mimimax approach, and its objective is to minimize the largest delay on any logical link, measured in both queueing delay and propagation delay. The problem is formulated as a 0/1 mixed integer programming and analyzed by decomposing it into two subproblems, called routing and dimensioning problems, for which an efficient hauristic algorithm is proposed in an iterating process made beween the two subproblems for solution improvement. The algorithm is tested for its performance eveluation.

The word error probability of linear block codes is computed for diversity systems with maximal ratio combining in mobile communications with three decoding algorithms: error correction (EC), error/erasure correction (EEC), and maximum likelihood (ML) soft decoding algorithm. Ideal interleaving is assumed. EEC gives 0.1-1.5dB gain over EC. The gain of EEC over EC decreases as the number of diversity channels increases. ML soft gives 1.8-5.5dB gain over EC.

This paper presents a new structure for noise and echo cancelers based on a combined fast abaptive algorithm. The main purpose of the new structure is to detect both the double-talk and the unknown path change. This goal is accomplished by using two adaptive filters. A main adaptive filter Fn, adjusted only in the non-double-talk period by the normalized LMS algorithm, is used for providing the canceler output. An auxiliary adaptive filter Ff, adjusted by the fast RLS algorithm, is used for detecting the double-talk and obtaining a near optimum tap-weight vector for Fn in the initialization period and whenever the unknown path has a sudden or fast change. The proposed structure is examined through computer simulation on a noise cancellation problem. Good cancellation performance and stable operation are obtained when signal is a speech corrupted by a white noise, a colored noise and another speech signal. Simulation results also show that the proposed structure is capable of distinguishing the near-end signal from the noise path change and quickly tracking this change.

This paper studies a video storage problem that occurs in Video-on-Demand (VOD) networks and in other distributed database systems. Videos should be stored in order to respect various constraints, especially available storage and transmission capacities. We show there exists an algorithm to solve this combinatorial problem through a pricing mechanism and that it converges to a solution under some general conditions. Simulation results with up to 43-node networks and up to 300 videos show that the algorithm is fast.

Currently there is considerable world-wide speculation regarding the introduction of optical fiber cable into access networks, because optical fiber has a big potential for providing attractive multimedia services. Since optical fiber cable can provide a variety of grade of services, high-reliability of cable networks would be required compared with the conventional copper cable networks. To develop multimedia telecommunication networks as an infrastructure, it is urgent to clarify the highly reliable optical fiber cable network architecture. Since cable network architecture deeply depends on regional conditions such as demand, area size, duct layer networks (consisting of ducts, manholes, tunnels, feeder points etc.), it is necessary to develop a cable network designing tool with user-friendly interfaces for efficiently evaluating cable network architectures. This paper firstly proposes the heuristic algorithms enhanced by the disjoint-shortest-path and the depth-first-search methods that would be applicable for real access networks. Secondly, the design method of highly reliable optical fiber cable network based on the heuristic algorithms in terms of network cost and unavailability caused by cable breakdown is proposed. It can design the combination of star- and loop-shaped (where two diversified routes exist between a feeder point and central office) cable network. Furthermore, comparison with the conventional design method which simply applies star- or loop-shaped cable network is done in terms of economy and reliability on real access networks in the Tokyo metropolitan area. It is concluded that the proposed method can reduce the network cost further and realize a short unavailability value compared with the conventional method.

The firing squad synchronization problem is considered for defective cellular automata. A lower bound of time tf for the problem is derived. The state complexity to solve the problem is investigated and it is shown that the state set has to be arbitrary large to obtain solutions of time complexity (n). For memory-augmented defective cellular automata a tf-time solution is given.

The selection of an appropriate key search algorithm for a specific application field is an important issue in application systems development. This is because data retrieval is the most time-consuming part of many application programs. An automatic selection method for key search algorithms is presented in this paper. The methodology has been implemented in a system called KESE2 (KEy-SEarch ALgorithm SElection). Key search algorithms are selected according to the user's requirements through interaction with KESE2 which bases its inferences on an evaluation table. This evaluation table contains values rating the performance of each key search algorithm for the different searching properties, or characteristics. The selection algorithm presented is based on step by step reduction of unsuitable key search algorithms and searching properties. The paper also proposes assistance facilities that consist of both a support function and a program synthesis function. Experimental results show that the appropriate key search algorithms are effectively selected, and that the necessary number of questions asked, to select the appropriate algorithm, is reduced to less than half of the total number of possible questions. The support function is useful for the user during the selection process and the program synthesis function fully translates a selected key search algorithm into high level language in an average of less than 1 hour.

We give an efficient shortest path algorithm on a mesh-connected processor array for nn banded matrices with bandwidth b. We use a b/2b/2 semisystolic processor array. The input data is supplied to the processor array from the host computer. The output from the processor array can be also supplied to itself through the host computer. This algorithm computes all pair shortest distances within the band in 7n4b/21 steps.

Two new algorithms for performing modular exponentiation are suggested. Nonstandard number systems are used. The first algorithm is based on the representing the exponent as a sum of generalized Fibonacci numbers. This representation is known as Zeckendorf representation. When precomputing is allowed the resulting algorithm is more efficient than the classical binary algorithm, but requires more memory. The second algorithm is based on a new number system, which is called hybrid binary-ternary number system (HBTNS). The properties of the HBTNS are investigated. With or without precomputing the resulting algorithm for modular exponentiation is superior to the classical binary algorithm. A conjecture is made that if more bases are used asymptotically optimal algorithm can be obtained. Comparisons are made and directions for future research are given.

Genetic algorithms have been shown to be very useful in a variety of search and optimization problems. In this paper, we propose a modified genetic channel router. We adopt the compatible crossover operator and newly designed compatible mutation operator in order to search solution space more effectively, where vertical constraints are integrated. By carefully selected fitness function forms and optimized genetic parameters, the current version speeds up benchmarks on average about 5.83 times faster than that of our previous version. Moreover the total convergence to optimal solutions for benchmarks can be always obtained.

In general, message passing multiprocessors suffer from communication overhead and shared memory multiprocessors suffer from memory contention. Also, data I/O overhead limits performance. In particular, computer vision tasks that require massive computation are strongly affected by these disadvantages. This paper proposes new parallel architectures for computer vision, a Flexibly (Tightly/Loosely) Coupled Multiprocessor (FCM) and a Flexibly Coupled Hypercube Multiprocessor (FCHM) to alleviate these problems. FCM and FCHM have a variable address space memory in which a set of neighboring memory modules can be merged into a shared memory by a dynamically partitionable topology. FCM and FCHM are based on two different topologies: reconfigurable bus and hypercube. The proposed architectures are quantitatively analyzed using computational models and parallel vision algorithms are simulated on FCM and FCHM using the Intel's Personal SuperComputer (iPSC), a hypercube multiprocessor, showing significant performance improvements over that of iPSC.

Given a sorted set S of n points in the plane, the prefix convex hulls problem of S is to compute the convex hull for every prefix set of S. We present a parallel algorithm for this problem. Our algorithm runs in O(logn) time using n/logn processors in the CREW PRAM computational model. The algorithm is shown to be time and cost optimal. One of the techniques we adopt to achieve these optimal bounds is the use of a new parallel data structure Array-Tree.

Real-time collision detection is one of the most important intelligent processings in robotics. In collision detection, a large storage capasity is usually required to store the 3-dimensional information on the obstacles located in a workspace. Moreover, high-computational power is essential in not only coordinate transformation but also matching operation. In the proposed collision detection VLSI processor, the matching operation is drastically accelerated by using a content-addressable memory (CAM). A new obstacle representation based on a union of rectangular solids is also used to reduce the obstacle memory capacity, so that the collision detection can be performed by only magnitude comparison in parallel. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speed, and each PE performs coordinate transformation at high speed based on the COordinate Rotation DIgital Computation (CORDIC) algorithms. When the 16 PEs and 144-kb CAM are used, the performance is evaluated to be 90 ms.

It is demonstrated that the enhancement in the functional capability of an elemental transistor is quite essential in developing human-like intelligent electronic systems. For this purpose we have introduced the concept of four-terminal devices. Four-terminal devices have an additional dimension in the degree of freedom in controlling currents as compared to the three-terminal devices like bipolar and MOS transistors. The importance of the four-terminal device concept is demonstrated taking the neuron MOS transistor (abbreviated as neuMOS or νMOS) and its circuit applications as examples. We have found that any Boolean functin can be realized by a two-stage configuratin of νMOS inverters. In addition, the variable threshold nature of the device allows us to build real-time reconfigurable logic circuits (no floating gate charging effect is involved in varying the threshold). Based on the principle, we have developed Soft-Hardware Logic Circuits and Real-Time Rule-Variable Data Matching Circuits. A winner-take-all circuit which finds the largest signal by hardware parallel processing has been also developed. The circuit is applied to building an associative memory which is different from Hopfield network in both principle and operation. The hardware algorithm in which binary, multivalue, and analog operations are merged at a very device level is quite essential to establish intelligent information processing systems based on highly flexible, real-time programmable hardwares realized by four-terminal devices.

We study robot navigation in unknown environment with rectangular obstacles aligned with the x and y axes. We propose a strategy called the modified-bian heuristic, and analyze its efficiency. Let n be the distance between the start point and the target of robot navigation, and let k be the maximum side length among the obstacles in a scene. We show that if k=(o(n) and if the summation of the widths of the obstacles on the line crossing the target and along the y axis is o(n), then ratio of the total distance walked by the robot to the shortest path length between the start point and the target is at most arbitrarily close to 1+k/2, as n grows. For the same restrictions as above on the sizes of the obstacles, the ratio is also at most arbitrarily close to 1+3/4n, as n grows, where is the summation of lengths of the obstacles in y axis direction.

Data of system parameters of real systems have some uncertainty and they should be given by sets (or intervals) rather than fixed values. To analyze and design systems contaning such uncertain parameters, it is required to represent and treat uncertainty in data of parameters, and to compute value sets of characteristic polynomials and transfer functions. Interval arithmetic is one of the most powerful tools to perform such subjects. In this paper, Polygon Interval Arithmetic (PIA) on the set of polygons in the complex plane is considered, and the data structure and algorithms to execute PIA efficiently is proposed. Moreover, practical examples are shown to demonstrate how PIA is useful to compute the evaluation of value sets.

A parallel quicksort algorithm in Ada is proposed and analyzed, its computational complexities are derived, and its performance profile is determined by simulation.