An efficient algorithm is presented for finding all solutions of piecewise-linear resistive circuits. In this algorithm, a simple sign test is performed to eliminate many linear regions that do not contain a solution. This makes the number of simultaneous linear equations to be solved much smaller. This test, in its original form, is applied to each linear region; but this is time-consuming because the number of linear regions is generally very large. In this paper, it is shown that the sign test can be applied to super-regions consisting of adjacent linear regions. Therefore, many linear regions are discarded at the same time, and the computational efficiency of the algorithm is substantially improved. The branch-and-bound method is used in applying the sign test to super-regions. Some numerical examples are given, and it is shown that all solutions are computed very rapidly. The proposed algorithm is simple, efficient, and can be easily programmed.

In this paper, a novel Y-junction type demultiplexer utilizing a stratified-waveguide configuration in the branching region is proposed for the purpose of improving the extinction ratio. A high extinction ratio of about 20 dB is achieved at 0.6328 µm and 0.83 µm operation wavelengths both for the TE and TM modes. The properties of the new type branchig waveguides which consist of the diffused waveguide and the striploaded waveguide are described to explain the operation principle. Simulation results by the BPM are also shown to check the designed values of the waveguide parameters.

The performance of ASIPs (Application Specific Integrated Processors) is heavily affected by the design of their instruction set architecture. In order to maximize the performance of ASIP, it is essential to design an architecture that has an optimum instruction set. This paper descibes a new method that automates the design of optimum instruction set of ASIP. This method solves the Instruction set implementation Method Selection Problem(IMSP). IMSP is to be solved in the instruction set architecture design. Frse, the IMSP is formalized as an integer programming problem, which is to maximize the perfomance of the CPU under the constraints of chip area and power consumption. Then, a branch-and-bound algorithm to solve IMSP is described. According to the experimental results, the proposed algorithm is quite effective and efficient in solving the IMSP. The presented method automates a complex part of the ASIP chip design and is also a good design tool that enables designer to predict the performance of their design before completion.

One of the most interesting and most analyzed aspects of the CPU design is the instruction set design. How many and which operations to be provided by hardware is one of the most fundamental issues relaing to the instruction set design. This paper describes a novel method that formulates the instruction set design of ASIP (an Application Specific Integrated Processor) using a combinatorial appoach. Starting with the whole set of all possible candidata instructions that represesnt a given application domain, this approach selects a subset that maximizes the performance under the constraints of chip area, power consumption, and functional module sharing relation among operations. This leads to the efficient implementation of the selected instructions. A branch-and-bound algorithm is used to solve this combinatorial optimization problem. This approach selects the most important instructions for a given application as well as optimizing the hardware resources that implement the selected instructions. This approach also enables designers to predict the perfomance of their design before implementing them, which is a quite important feature for producing a quality design in reasonable time.

We report on 1N branching devices for fiber-optic networks. A novel Y-pattern mask for loss reduction in branching waveguide has been investigated based on simulation. 18 branching waveguides fabricated by ion-exchange proved that the scattering loss at the branching region made with novel Y-pattern is reduced considerably. Pigtailing technique has been developed using glass fiber arrays (FAs). The fibers in FA are aligned precisely, so that all fibers can be easily and precisely put into alignment with the output ports in a branching waveguide chip at the same time. A glass plate is used for reinforcement which improves mechanical and thermal stability of the device. Reliability of packaged devices is being strongly demanded. Various reliability tests have been performed with packaged 18 branching devices and those results are presented.

Networks in this paper consist of non-commensurate transmission lines with branches and branching resistors at junctions. When signals on a transmission line are divided multiple ways at the junctions of branched lines, multiple reflection waves occur by the impedance mismatching. For the analysis of multiple reflections and network design, lattice diagrams have been used so far. However, the expansions of network transfer functions provide an easier way for the same purpose as in the case of lattice diagram. The output transient responses can be directly calculated from the expansions of network transfer functions or can be numerically calculated by software such as the fast Laplace transform. Therefore, once the network transfer functions are given, calculation of transient responses can be carried out quite easily. In this paper, the expansions of network transfer functions have been derived with respect to delay elements ξi=exp(-sτi) by formularizing the propagation of multiple reflection waves, and then the multi-variable rational network transfer functions have been obtained from the expansions. As an example, a 3-port transmission line network with normalized characteristic impedances 1, 1, 6 and normalized branching resistors 1/23, 1/23, 126/23 has been taken up. As the terminal resistances at output ports can be determined from the relation of the first arriving wave to the steady state, the design of 3-port transmission line networks which will furnish output waveforms similar to the waveform of the input within given tolerances has been considered. The output waveforms have been calculated for pure terminal resistances and for the pure terminal resistances plus parasitic parallel capacitances.