In this paper, the characteristics of a micro DC-DC converter for portable electronic equipments are described. In the converter, an inductor, switching devices and control integrated circuits (ICs) were integrated. The external size of the converter module was 3.0 mm 3.0 mm 1.0 mm. And the converter had a high efficiency of 83% at the input voltage of 7.2 V and the output voltage of 1.5 V. The miniaturization of the converter was achieved by developing a small inductor of the size of 3.0 mm 3.0 mm 0.525 mm. High efficiency was achieved by adopting 0.6 µm CMOS process for ICs and switching devices, using N channel MOSFET for a high side power switch, and controlling a dead time adaptively. The efficiency characteristics of the converter were analyzed experimentally and theoretically. And the losses of the converter were theoretically analyzed.

The metal/ferroelectric material/metal/oxide insulating material/Si substrates (MFMIS) structure was realized by using Pb(Zr0. 4Ti0. 6)O3 (PZT) thin film. PZT(330 nm thick) thin film was sandwiched between the upper electrode of Ti/Pt-Rh (about 380 nm thick and 123 microns in diameter) and the lower electrode of Pt-Rh/Ti (about 380 nm thick and 378 microns in diameter). The MFM structures mentioned above were prepared on metal oxide semiconductor (MOS structures). Pt-Rh and Ti lower electrodes were directly deposited on a poly-Si MOS electrode with sputtering, and PZT layer was prepared using the sol-gel method. In order to maximize induced charge density in the MOS gate, diameters of the upper and the lower electrodes were adjusted, and the MFM area-to-MOS area ratio was optimized. By using the area ratio of 0. 11 a memory window of 2. 4 V was obtained.

Circuit performance of SiC-MOSFET-based bidirectional isolated DC/DC converters is investigated based on circuit simulation with the physically accurate compact device model HiSIM_HV. It is demonstrated that the combined optimization of the MOSFETs Ron and of the inductances in the transformer can enable a conversion efficiency of more than 97%. The simulation study also verifies that the possible efficiency improvements are diminished due to the MOSFET-performance degradation, namely the carrier-mobility reduction, which results in a limitation of the possible Ron reduction. It is further demonstrated that an optimization of the MOSFET-operation conditions is important to utilize the resulting higher MOSFET performance for achieving additional converter efficiency improvements.

The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.

A newly developed planar inductor and its application to dc-dc converters are described. The planar inductor consists of a planar spiral coil and soft magnetic sheets, it has a small size (11110.8mm), 33µH inductance and a maximum quality factor of 14. The step down chopper dc-dc converter has been developed by using planar inductor, which has small size (20154mm), 5V-2W typical output and output power/volume ratio of 1.7W/cc. The switching converter can be miniaturized by using the planar inductor.

We report on 1N branching devices for fiber-optic networks. A novel Y-pattern mask for loss reduction in branching waveguide has been investigated based on simulation. 18 branching waveguides fabricated by ion-exchange proved that the scattering loss at the branching region made with novel Y-pattern is reduced considerably. Pigtailing technique has been developed using glass fiber arrays (FAs). The fibers in FA are aligned precisely, so that all fibers can be easily and precisely put into alignment with the output ports in a branching waveguide chip at the same time. A glass plate is used for reinforcement which improves mechanical and thermal stability of the device. Reliability of packaged devices is being strongly demanded. Various reliability tests have been performed with packaged 18 branching devices and those results are presented.