Due to the slowdown of Moore's Law, power limitation has been one of the most critical issues for current and future HPC systems. To more efficiently utilize HPC systems when power budgets or deadlines are given, it is very desirable to accurately estimate the performance or power consumption of applications before conducting their tuned production runs on any specific systems. In order to ease such estimations, we showcase a straight-forward and yet effective method, based on the enhanced power management framework and DSL we developed, to help HPC users to clarify the performance and power relationships of their applications. This method demonstrates an easy process of profiling, modeling and management on both performance and power of HPC systems and applications. In our evaluations, only a few (up to 3) profiled runs are necessary before very precise models of HPC applications can be obtained through this method (and algorithm), which has dramatically improved the efficiency of and lowered the difficulty in utilizing HPC systems under limited power budgets.

A stacked structure consisting of ∼ 1 nm-thick MgO and ∼ 4 nm-thick HfO2 was formed on thermally grown SiO2/Si(100) by MOCVD using dipivaloymethanato (DPM) precursors, and the influences of N2 anneal on interfacial reaction and defect state density in this stacked structure were examined. The chemical bonding features of Mg atom were evaluated by using an Auger parameter independently of positive charge-up during XPS measurements. With Mg incorporation into HfO2, a slight decrease in the oxidation number of Mg was detectable. The result suggests that Mg atoms are incorporated preferentially near oxygen vacancies in the HfO2, which can be responsible for a reduction of the flat band voltage shifts observed from C-V characteristics.

A novel NiSi technology with bi-layer Co/TiN structure as a capping layer is proposed for the highly thermal immune Ni Silicide technology. Much better thermal immunity of Ni Silicide was certified up to 700, 30 min post silicidation furnace annealing by introducing Co/TiN bi-layer capping. The proposed structure is successfully applied to nano-scale CMOSFET with a gate length of 80 nm. The sheet resistance of nano-scale gate poly shows little degradation even after the high temperature furnace annealing of 650, 30 min. The Ni/Co/TiN structure is very promising for the nano-scale MOSFET technology which needs the ultra shallow junction and high temperature post silicidation processes