Support of incoming traffic differentiation and Quality of Service (QoS) assurance is very important for the development of high performance packet switches, capable of separating traffic flows. In our previous paper, we proposed the implementation of two buffers at each crosspoint of a crossbar fabric that leads to the Dual Crosspoint Queued (DCQ) switch. Inside DCQ switch, one buffer is used to store the real-time traffic and the other for the non-real-time traffic. We also showed that the static priority algorithms can provide the QoS only for the real-time traffic due to their greedy nature that gives the absolute priority to that type of traffic. In order to overcome this problem, in our paper we propose the DCQ switch with the Largest Weighted Occupancy First scheduling algorithm that provides the desired QoS support for both traffic flows. Detailed analysis of the simulation results confirms the validity of proposed solution.

A shared buffer ATM switch loaded with bursty input traffic is modeled by a discrete-time queueing system. Also, the unbalanced and correlated routing traffic patterns are considered. An approximation method to analyze the queueing system under consideration is developed. To overcome the problem regarding the size of state space to be dealt with, the entire switching system is decomposed into several subsystems, and then each subsystem is analyzed in isolation. We first propose an efficient algorithm for superposing all the individual bursty cell arrival processes to the switch. And then, the maximum entropy method is applied to obtain the steady-state probability distribution of the queueing system. From the obtained steady-state probabilities, we can derive some performance measures such as cell loss probability and average delay. Numerical examples of the proposed approximation method are given, which are compared with simulation results.

We propose a new approach to the exact performance analysis of a shared buffer ATM multiplexer, which is loaded with mixed correlated and uncorrelated traffic sources. We obtain the joint steady-state probabilities of both states of the input process and the buffer using a one-dimensional Markov chain. From these probabilities we calculate the loss probabilities and the average delays of the correlated and the uncorrelated traffic sources.

Input and output queueing two stage ATM switch model which is effective under variable hot-spot traffic is proposed. In order to prevent the degradation of performance due to hot-spot traffic, the hot-spot route is added in which cells destined to the hot-spot port bypass. The switch applies the backpressure mode basically. When the switch judges that the hot-spot port exists, it routes cells destined there to the hot-spot route and applies the queue loss mode on them. We evaluate both the cell loss probability and the mean system delay under the nonuniform traffic with variable hot-spot port by computer simulation. As the results, it is shown that our proposed switch can achieve better switching performance than those of conventional switches under variable traffic condition.

Superposed ATM cell streams have burstiness and strong autocorrelation properties. This paper investigates traffic measurement-based modeling method for superposed ATM cell streams. We develop a new measurement method based on monitoring both the waiting time distribution in a monitoring queue and the autocorrelation of cell interarrival times. Through the monitoring queue, we directly observe the queueing effect of superposed cell flows on ATM multiplexers. The measured traffic is modeled as the two-state MMPP. With the measured traffic, we estimate the cell loss probability in ATM multiplexers from the MMPP/D/1/K queue. Our method successfully works with homogeneous and heterogeneous superposition of traffic sources including voice, data, and video. These results can be applied to the evaluation of ATM multiplexers, traffic engineering, and network performance monitoring.

Many ATM switching modules with high performance have been proposed and analyzed. A development of a large scale ATM switching system (e.g., used as a central switch) is the key to realization of the broadband ISDN. However, the dimension of ATM switching ICs is limited by the technological and physical constraints on VLSI. A multistage switching configuration is one of the promising configurations for a large scale ATM switch. In this paper, we treat a 3-stage switching configuration with no internal bufferes; i.e., bufferless switches are employed at the first and second stages, and output buffered switches at the third stage. A short-term cell loss probability is analyzed in order to examine the influence of bursty traffic on performance of the bufferless switch used at the first two stages. Furthermore, we propose a 4-stage switching configuration with traffic distributors added at the first stage. This switch provides more paths between a pair of input and output ports than the 3-stage switching configuration mentioned above. A few schemes to distribute cells are compared. It is shown that the distributor successfully reduces the deterioration of cell loss probability due to bursty traffic by splitting incoming cells into several switching modules.

This letter describes the High-speed Statistical Retry switch (HSR switch) for high-speed ATM switching systems. The HSR switch uses a new matrix-shaped switching structure with buffers at input and ouptut ports, and a simple retry algorithm. The input buffers are very small, and no complicated arbitration function is employed. A cell is repeatedly transmitted from each input buffer at m times the input line speed until the input buffer receives an acknowledge signal from the intended output buffer. A maximum of one cell can be transmitted from each input buffer during the cell transmission time. The internal ratio (m) is decided according to the probability of cell conflict in the output line. Simulation results show that just a 10-cell buffer at each input port and a 50-cell buffer at each output port are required when m=4 to achieve a cell loss probability of better than 10-8, irrespective of the switch size. At each crosspoint, cells on the horizontal input line take precedence over those on the vertical input line. Only a very simple retry algorithm is employed, no complex arbitration is needed, and the arbitration circuit at the crosspoint can be reduced by about 90% in size. The proposed ATM switch architecture is applicable to high-speed (Gbit/s) ATM switches for B-ISDN because of its simplicity.

This paper analyzes the performance of an ATM cell multiplexer with a two level MMPP input on a discrete-time basis. We approximated the input process as a simple MMPP model. We developed an MMPP/D/1/K queueing model for the ATM cell multiplexer, and employed an analytic approach for the evaluation of cell loss probability. We verified the accuracy of the results using computer simulation. We applied the above analytic method to connection admission control (CAC) of the ATM network. The resulting connection admission control scheme employs the concept of the "effective bandwidth" and table-look-up procedure. We confirmed through a computer simulation that the proposed connection admission control scheme outperforms the peak bandwidth allocation scheme with respect to link utilization.