This paper presents a new low-dropout (LDO) regulator with low-quiescent, high-drive and fast-transient performance. This is based on a new composite power transistor composed of a shunt feedback class-AB embedded gain stage and the application of dynamic-biasing schemes to both the error amplifier as well as the composite power transistor. The proposed LDO regulator has been simulated and validated using BSIM3 models and GLOBALFOUNDRIES 0.18-µm CMOS process. The simulation results have shown that the LDO regulator consumes 4.7 µA quiescent current at no load, regulating the output at 1 V from a minimum 1.2 V supply. It is able to deliver up to 450 mA load current with a dropout of 200 mV. It can be stabilized using a 4.7 µF output capacitor with a 0.1 Ω ESR resistor. The maximum transient output voltage is 64.6 mV on the basis of a load step change of 450 mA/10 ns under typical condition. The full load transient response is less than 350 ns.

In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102 dB DC gain, and a 37.6 MHz unity gain bandwidth while driving a 2 nF heavy capacitive load at a single 1.8 V supply. In the comparison of power-bandwidth and power-speed efficiencies on figures of merit, it offers significantly high values with respect to the reported state-of-the-art works. By employing the composite transistor in a linear regulator powered by a 3.3 V supply to generate a 1.8 V output voltage, it has shown fast recovery response at various load current transients, having a 1% settling time of 0.1 µS for a 50 mA or 100 mA step, while a 1% settling time of 0.36 µS for a maximum 735 mA step under a capacitive load of 10 µF with a 1 Ω ESR resistor. The simulated load regulation is 0.035% and line regulation is 0.488%. Comparing its results with other state-of-art LDO reported results, it also validates the significant enhanced performance of the proposed composite-transistor-based design in terms of speed, current driving capability and stability against changes in environmental parameters. All the proposed designs are simulated using chartered semiconductor (CSM) 1.8 V/3.3 V 0.18 µm CMOS triple-well process technology with thin/thick oxide options and BSIM3 model parameters.

This work presents an ultra-low-voltage ultra-low-power weak inversion composite MOS transistor. The steady state power consumption and the linear swing signal of the composite transistor are comparable to a single transistor, whereas presenting very high output impedance. This work also presents two interesting applications for the composite transistor; a 1:1 current mirror and an extremely low power temperature sensor, a thermistor. Both implementations are verified in a standard 0.35-µm TSMC CMOS process. The current mirror presents high output impedance, comparable to the cascode configuration, which is highly desirable to improve gain and PSRR of amplifiers circuits, and mirroring relation in current mirrors.

A design of a low-power CMOS ring oscillator for an application to a 13.56 MHz clock generator in an implantable RFID tag is proposed. The circuit is based on a novel voltage inverter, which is an improved version of the conventional current-source loaded inverter. The proposed circuit enables low-power operation and low sensitivity of the oscillation frequency, fOSC, to decay of the power supply VDD. By employing a gm-boosting subcircuit, power dissipation is decreased to 49 µW at fOSC=13.56 MHz. The sensitivity of fOSC to VDD is reduced to -0.02 at fOSC=13.56 MHz thanks to the use of composite high-impedance current sources.

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |Vt|+2 Vds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2µm N-well process with a 3 V supply are given.