EMV signature is one of specifications for authenticating credit and debit card data, which is based on ISO/IEC 9796-2 signature scheme. At CRYPTO 2009, Coron, Naccache, Tibouchi, and Weinmann proposed a new forgery attack against the signature ISO/IEC 9796-2 (CNTW attack) [2]. They also briefly discussed the possibility when the attack is applied to the EMV signatures. They showed that the forging cost is $45,000 and concluded that the attack could not forge them for operational reason. However their results are derived from not fully analysis under only one condition. The condition they adopt is typical case. For security evaluation, fully analysis and an estimation in worst case are needed. This paper shows cost-estimation of CNTW attack against EMV signature in detail. We constitute an evaluate model and show cost-estimations under all conditions that Coron et al. do not estimate. As results, this paper contribute on two points. One is that our detailed estimation reduced the forgery cost from $45,000 to $35,200 with same condition as [2]. Another is to clarify a fact that EMV signature can be forged with less than $2,000 according to a condition. This fact shows that CNTW attack might be a realistic threat.

We propose an efficient selective block encoding scheme with motion information feedback in distributed video coding (DVC). The proposed scheme estimates the spatial and temporal matching costs for each block in the side information (SI) and for the blocks with high matching costs, the motion information is provided to the encoder side to selectively encode the motion-compensated frame difference signal. Experimental results show that the proposed scheme outperforms the recently developed DVC algorithms.

The aim of this paper is to present a new cost estimation technique to synthesis hardware from high level circuit description. The scheduling and allocation processes are performed in alternative manner, while using realistic cost measurements models that account for Functional Unit (FU), registers, and multiplexers. This is an improvement over previous works, were most of them use very simple cost models that primarily focus on FU resources alone. These latest, however, are not accurate enough to allow effective design space exploration since the effects of storage and interconnect resources can indeed dominates the cost function. We tested our technique on several high-level synthesis benchmarks. The results indicate that the tool can generate near-optimal bus-based and multiplexer-based architectural models with lower number of registers and buses, while presenting high throughput.

This paper presents an enhancement of a software project simulator to perform risk prediction with cost estimation capability. So far, we have developed a software project simulator to simulate software development projects. In this simulator, a development process was described using Petri net model, and it was applied to some actual project data in a certain company successfully. On the other hand, we have also presented a risk predicting system to find "risky" projects by statistical analysis on risk questionnaire for project managers. In this approach, only the probability to be risky was calculated for a project. Thus, the managers in the company wanted to know a concrete proof why a software project becomes risky. In this paper, to present the proof that a software project becomes risky, we try to enhance the previous project simulator so that the simulator can deal with risk factors. To consider the risk factors, we modify the previous simulator so that both the fluctuation of skill level and the deadline pressure can be represented by the parameters in the simulator. By using a case study, we confirm that the enhanced simulator can estimate the development cost under some typical risks. As a result, we can expect that the simulator shows how much the development cost of a risky project exceeds an estimate.