An Ldi/dt effect model based on float ground in a plamsa display panel (PDP) driver system is established in this paper. The model is to analyze the noise which appears in power supply and float ground pins of driver integrated circuits. Considering printed circuit board wiring and switching parasitic parameters, firstly Ldi/dt effect due to integrated circuits transition, is explained on the entire float-ground circuit operation. Then an analytic model is deduced and validated, and good agreement is obtained with experimental results. Based on the model, sensitivity analyses of key parameters are done. Finally, design optimisations to prevent the Ldi/dt effect based on float ground are proposed and verified in a PDP system.

This paper demonstrates an autonomous di/dt control of power supply for margin aware operation. A di/dt on the power line is detected by a mutual inductor, the induced voltage is multiplied by Gilbert multiplier and the following low pass filter outputs a DC voltage in proportion to the di/dt. The DC voltage is compared with reference voltages, and the modes of the internal circuit is controlled depending on the comparators output. By using this scheme, the di/dt noise power can be autonomously controlled to fall within a defined range set by the reference voltages. Our experimental results show that the internal circuit oscillates between the all-active and the half-active modes, also show that the all/half ratio and the oscillation frequency changes depending on the reference voltages. It proves that our autonomous di/dt noise control scheme works as being designed.

This paper demonstrates a feedforward active substrate noise cancelling technique using a power supply di/dt detector. Since the substrate is usually tied with the ground line with a low impedance, the substrate noise is closely related to the ground bounce which is proportional to the di/dt when inductance is dominant on the ground line impedance. Our active cancelling detects the di/dt of the power supply, and injects an anti-phase current into the substrate so that the di/dt-proportional substrate noise is cancelled out. Our first trial shows that 34% substrate noise reduction is achieved on our test circuit, and the theoretical analysis shows that the optimized canceller design will enhance the substrate noise suppression ratio up to 56%.

This paper demonstrates a power supply noise reduction using on-board stubs. A quarter-length stub attached to the power supply line of an LSI chip works as a band-eliminate filter, and suppresses the power supply noise of the designed frequency. Preliminary experiments show that 87% of the designed frequency noise component is suppressed when stub patterns are written on a power supply area on a PCB board for a 1.25 GHz operating LSI. The results show the possibility of the stub on-chip integration when the operating frequency of LSIs becomes higher and the stub length becomes shorter.

This paper demonstrates an on-chip di/dt detector circuit. The di/dt detector circuit consists of a power supply line, an underlying spiral inductor and an amplifier. The mutual inductor induces a di/dt proportional voltage, and the amplifier amplifies and outputs the value. The measurement results show that the di/dt detector output and the voltage difference between a resistor have good agreement. The di/dt reduction by a decoupling capacitor is also measured using the di/dt detector.

This paper compares a stub and a decoupling capacitor for power supply noise reduction. A quarter-length stub attached to the power supply line of an LSI chip works as a band-eliminate filter, and suppresses the power supply bounce of the designed frequency. The conditions where the stub is more effective than the same-area decoupling capacitor are clarified. The stub will work more efficiently and on-chip integration will be possible on high frequency operation LSIs.

This paper demonstrates the slope isn't an appropriate parameter to characterize a signal regarding conducted electromagnetic disturbances. On the other hand, a relevant criterion is made conspicuous: it defines the maximum slope deviation between two segments forming a signal. This criterion is validated by a signal with a maximum slope of 400 mA/µs.