We present self-calibration techniques for an interleaved SAR (Successive Approximation Register) ADC. The calibration technique is based on hardware corrections for linearity of single stage, gain error and mismatch errors of parallel ADCs. The 4-interleaved 11-bit ADC has been fabricated in a 0.18-µm CMOS process. Using the calibrations, measurement and calculation results show that the differences of ramp characteristic among the 4-interleaving ADC can be decresased to under 0.63 LSB.

We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital control blocks has been fabricated in a 0.18-µm CMOS process and consumes 118 µW at 1.8 V power supply. Also, the active area of ADC core is realized to be 0.027 mm2. The calibration improves the SNDR by 13.4 dB and the SFDR by 21.0 dB. The measured SNDR and SFDR at 1 kHz input are 55.2 dB and 73.2 dB respectively.

This paper analyzes the spurious sources in DDS synthesizers and deduces the simple model of DDS output signal. The method of feeding pseudo-random noise into the phase accumulator for spurious reduction is discussed. A new method for spurious reduction by compensating for DAC integer nonlinearity is proposed with two DACs and a power combiner. One DAC generates the error signal to compensate for the other DAC INL. The factor how the amplitude error and the phase error between the two combined signals affect the spurious level is also analyzed. The experiment shows that the spurious reduction can be improved by at least 18 dB, which proves the validity of the DAC INL compensation method for the spurious reduction.