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[Keyword] divide-by-3(3hit)

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  • Divide-by-3 Injection-Locked Frequency Divider Using Two Linear Mixers

    Sheng-Lyang JANG  Cheng-Chen LIU  Jhin-Fang HUANG  

     
    BRIEF PAPER-Electronic Circuits

      Vol:
    E93-C No:1
      Page(s):
    136-139

    This paper proposes a wide-locking range divide-by-3 injection-locked frequency divider (ILFD) fabricated in the 90 nm 1P9M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled nMOSFETs. The ILFD is formed with two linear mixers which share the same dc current so that a low power ILFD can be designed. At the supply voltage of 0.7 V, the free-running frequency is from 10.18 to 11.56 GHz, the current and power consumption of the divider without buffers are 2.8 mA and 1.96 mW, respectively. At the incident power of 0 dBm, the total operational locking range is 4.94 GHz, from the incident frequency 29.96 to 34.9 GHz.

  • Divide-by-3 LC Injection Locked Frequency Divider Implemented with 3D Inductors

    Sheng-Lyang JANG  Chia-Wei CHANG  Chien-Feng LEE  Jhin-Fang HUANG  

     
    PAPER-Electronic Circuits

      Vol:
    E91-C No:6
      Page(s):
    956-962

    This paper proposes a wide-locking range divide-by-3 frequency divider employing 3D helical inductors fabricated in the 0.18-µm 1P6M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled NMOSFETs, and the LC resonator is composed of two 3D helical inductors and varactors. The aim of using 3D inductor is to reduce chip size. At the supply voltage of 1.2 V, the divider free-running frequency is tunable from 2.1 GHz to 2.6 GHz, and at the incident power of 0 dBm the locking range is about 2.11 GHz (29.16%), from the incident frequency 5.99 GHz to 8.1 GHz. The core power consumption is 4.56 mW. The die area is 0.6640.831 mm2.

  • True 50% Duty-Cycle SSH and SHH SiGe BiCMOS Divide-by-3 Prescalers

    Sheng-Che TSENG  Chinchun MENG  Wei-Yu CHEN  

     
    PAPER

      Vol:
    E89-C No:6
      Page(s):
    725-731

    Four 50% duty-cycle divide-by-3 prescalers--positively/ negatively triggered sample-sample-hold (SSH) and sample-hold-hold (SHH) prescalers--are designed based on the current switchable D flip-flops and discussed in this paper. The positively triggered SSH and SHH prescalers are fabricated using the 0.35-µm SiGe BiCMOS technology and measured by the real-time oscilloscope and the spectrum analyzer. The SHH prescaler is our proposed structure and demonstrated in this paper. According to the measurement results, under the condition of the same input power, its maximum operation frequency is twice as high as that of the SSH prescaler thanks to better signal synchronization. At 2.7 V supply, the SSH prescaler operates from 500 MHz to 2 GHz as the SHH prescaler performs from 1 GHz to 3.4 GHz. The input sensitivity level of both structures is about -5 dBm, while the maximum output power is also about -5 dBm. The core current consumption is 4.538 mA and 4.258 mA for the SSH and SHH prescalers, respectively.