In this study, the effect of nitrogen-doped (N-doped) LaB6 bottom-contact electrodes and interfacial layer (IL) on n-type pentacene-based organic field-effect transistor (OFET) was investigated. The scaled OFET was fabricated by using photolithography for bottom-contact electrodes. A 20-nm-thick N-doped LaB6 bottom-contact electrodes were formed on SiO2/n+-Si(100) substrate by RF sputtering followed by the surface treatment with sulfuric acid and hydrogen peroxide mixture (SPM) followed by diluted hydrofluoric acid (DHF; 1% HF) at room temperature (RT). Then, a 1.2-nm-thick N-doped LaB6 IL was deposited at RT. Finally, a 10-nm-thick pentacene film was deposited at 100°C followed by the Al back-gate electrode formation by using thermal evaporation. The current of electron injection was observed in the air due to the effect of surface treatment and N-doped LaB6 IL.

Three types of electron injection scheme: both side injection scheme and self-repair one side injection scheme Type A (injection for once) and Type B (injection for twice) are proposed and analyzed comprehensively for 65 nm technology node 6T- and 8T-SRAM cells to find the optimum injection scheme and cell architecture. It is found that the read speed degrades by as much as 6.3 times in the 6T-SRAM with the local injected electrons. However, the read speed of the 8T-SRAM cell does not degrade because the read port is separated from the write pass gate transistors. Furthermore, the self-repair one side injection scheme is most suitable to solve the conflict of the half select disturb and write characteristics. The worst cell characteristics of Type A and Type B self-repair one side injection schemes were found to be the same. In the self-repair one side injection 8T-SRAM, the disturb margin increases by 141% without write margin or read speed degradation. The proposed schemes have no process or area penalty compared with the standard CMOS-process.

This paper discusses crystal-growth and device-design issues associated with the development of high-performance InP/InGaAs heretostructure bipolar transistors (HBTs). It is shown that a highly Si-doped n+-subcollector in the HBT structure causes anomalous Zn redistribution during metalorganic vapor phase epitaxial (MOVPE) growth. A thermodynamical model of and a useful solution to this big problem are presented. A novel hybrid structure consisting of an abrupt emitter-base heterojunction and a compositionally-graded base is shown to enhance nonequilibrium base transport and thereby increase current gain and cutoff frequency fT. A double-heterostructure bipolar transistor (DHBT) with a step-graded InGaAsP collector can improve collector breakdown behavior without any speed penalty. We also elucidate the effect of emitter size shrinkage on high-frequency performance. Maximum oscillation frequency fmax in excess of 250 GHz is reported.

An efficient method which integrates a 2-D energy transport model, impact ionization model, gate current model, a discretized gate-capacitor EPROM model, and a post-processing quasi-transient programming/erase method, was developed for deep-submicron EPROM/Flash device simulation. The predicted results showed on the average better than 90% accuracy, and it took only few minutes CPU time on a SUN/SPARC2 to generate EPROM/Flash Vt shift curves.