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Yang XIAO Zhongyuan ZHOU Mingjie SHENG Qi ZHOU
The method of extracting impedance parameters of surface mounted (SMD) electronic components by test is suitable for components with unknown model or material information, but requires consideration of errors caused by non-coaxial and measurement fixtures. In this paper, a fixture for impedance measurement is designed according to the characteristics of passive devices, and the fixture de-embedding method is used to eliminate errors and improve the test accuracy. The method of obtaining S parameters of fixture based on full wave simulation proposed in this paper can provide a thought for obtaining S parameters in de-embedding. Taking a certain patch capacitor as an example, the S parameters for de-embedding were obtained using methods based on full wave simulation, 2×Thru, and ADS simulation, and de-embedding tests were conducted. The results indicate that obtaining the S parameter of the testing fixture based on full wave simulation and conducting de-embedding testing compared to ADS simulation can accurately extract the impedance parameters of SMD electronic components, which provides a reference for the study of electromagnetic interference (EMI) coupling mechanism.
Takuya WADATSUMI Kohei KAWAI Rikuu HASEGAWA Kikuo MURAMATSU Hiromu HASEGAWA Takuya SAWADA Takahito FUKUSHIMA Hisashi KONDO Takuji MIKI Makoto NAGATA
This paper presents on-chip characterization of electrostatic discharge (ESD) impacts applied on the Si-substrate backside of a flip-chip mounted integrated circuit (FC-IC) chip. An FC-IC chip has an open backside and there is a threat of reliability problems and malfunctions caused by the backside ESD. We prepared a test FC-IC chip and measured Si-substrate voltage fluctuations on its frontside by an on-chip monitor (OCM) circuit. The voltage surges as large as 200mV were observed on the frontside when a 200-V ESD gun was irradiated through a 5kΩ contact resistor on the backside of a 350μm thick Si substrate. The distribution of voltage heights was experimentally measured at 20 on-chip locations among thinned Si substrates up to 40μm, and also explained in full-system level simulation of backside ESD impacts with the equivalent models of ESD-gun operation and FC-IC chip assembly.