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[Keyword] hot carriers(2hit)

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  • Comparison between Device Simulators for Gate Current Calculation in Ultra-Thin Gate Oxide n-MOSFETs

    Eric CASSAN  Sylvie GALDIN  Philippe DOLLFUS  Patrice HESTO  

     
    PAPER-Gate Tunneling Simulation

      Vol:
    E83-C No:8
      Page(s):
    1194-1202

    The gate oxide of sub-0.1 µm MOSFETs channel length is expected to be reduced beyond 3 nm in spite of an increasing direct tunneling gate current. As tunnel injection modeling into SiO2 is expected to depend on the electron transport model adopted for the device description, a critical comparison is made in this paper between gate currents obtained from simulators based on Drift-Diffusion, Energy-Balance, and Monte Carlo models. The studied device is a 0.07 µm channel length n-MOSFET with 1.5 nm thick gate oxide. It is shown that positive drain voltage is responsible for two opposite effects on DT leakage: a carrier heating and a potential barrier hardening along the channel. It is proved by a careful study of Monte Carlo microscopic quantities that, contrary to what holds for thicker gate oxide transistors, the balance is favorable to the potential barrier effect. Injection into SiO2 is then dominated by near-thermal carriers injected at the channel beginning. For this reason, the gate current decreases when increasing the drain bias, with the maximum leakage obtained for (Vgs=Vdd, Vds=0), and a correct agreement is obtained between the Drift-Diffusion, Energy-Balance, and Monte Carlo approaches of gate current calculation, in spite of very different physical descriptions of transport at the microscopic level.

  • A Study on Hot-Carrier-Induced Photoemission in n-MOSFETs

    Toshihiro MATSUDA  Naoko MATSUYAMA  Kiyomi HOSOI  Etsumasa KAMEDA  Takashi OHZONE  

     
    PAPER

      Vol:
    E82-C No:4
      Page(s):
    593-601

    Profiles of photoemission induced by hot electrons in LDD-type n-MOSFETs with L = 0.35-2.0 µm were measured with a photoemission microscope, which had a capability of 1000 magnification and a spatial resolution of 27 nm/pixel on a CCD imager sufficient to detect profile changes in the channel length direction. Under the bias condition of maximum substrate current, photoemission peaks were located at the LDD-drain edge and the n+-drain edge for the devices with L = 0.35 and L 0.40 µm, respectively. A peak position, only in the case of the 0.35 µm device, shifted toward the drain side by about 80 nm at VD = 7.0 V. Since VD did not affect peak positions in L 0.40 µm devices, the photoemission mechanisms may be different between L = 0.35 µm and L 0.40 µm devices. The photoemission points due to p-n junction breakdown were located at the cylindrical curvature edge of the n+-drain region. Two-dimensional device simulation, even when the lateral electric field, electron temperature and radiative recombination rate were taken into account, could not explain the experimental results completely.