Software defect prediction (SDP) plays a vital role in allocating testing resources reasonably and ensuring software quality. When there are not enough labeled historical modules, considerable semi-supervised SDP methods have been proposed, and these methods utilize limited labeled modules and abundant unlabeled modules simultaneously. Nevertheless, most of them make use of traditional features rather than the powerful deep feature representations. Besides, the cost of the misclassification of the defective modules is higher than that of defect-free ones, and the number of the defective modules for training is small. Taking the above issues into account, we propose a cost-sensitive and sparse ladder network (CSLN) for SDP. We firstly introduce the semi-supervised ladder network to extract the deep feature representations. Besides, we introduce the cost-sensitive learning to set different misclassification costs for defective-prone and defect-free-prone instances to alleviate the class imbalance problem. A sparse constraint is added on the hidden nodes in ladder network when the number of hidden nodes is large, which enables the model to find robust structures of the data. Extensive experiments on the AEEEM dataset show that the CSLN outperforms several state-of-the-art semi-supervised SDP methods.

It is shown that an infinite lumped-element LC- ladder network generates all Bessel functions Jn(t) of the first kind as a response to a single non-zero initial condition. Closed-form expressions for the voltage responses in the time domain are presented if the LC- ladder is driven by a step-like input voltage.

Distortion characteristics caused by the thermal memory effect in power amplifiers were accurately predicted using a multi-stage thermal RC-ladder network derived by simplifying the heat diffusion equation. Assuming a steep gradient of heat diffusion near an intrinsic transistor region in a semiconductor substrate, the steady state temperature, as well as the transient thermal response at the transistor region, was estimated. The thermal resistances and thermal capacitances were adjusted to fit a temperature distribution characteristic and a step response characteristic of temperature in the substrate. These thermal characteristics were calculated by thermal FDTD simulation. For an InGaP/GaAs HBT, a step response characteristic for a square-wave voltage signal input was simulated using a large-signal model of the HBT connecting the multi-stage thermal RC-ladder network. The result was verified experimentally. Additionally, for an RF-amplifier using the HBT, the 3rd-order intermodulation distortion caused by the thermal memory effect was simulated and this result was also verified experimentally. From these verifications, a multi-stage thermal RC-ladder network can be used to accurately design super linear microwave power amplifiers and linearizers.