We have investigated post-metallization annealing (PMA) utilizing TiN gate electrode on the thin ferroelectric undoped HfO2 directly deposited on p-Si(100) by RF magnetron sputtering. By post-deposition annealing (PDA) process at 600°C/30 s in N2, the memory window (MW) in the C-V characteristics was observed in the Al/HfO2/p-Si(100) diodes with 15 to 24-nm-thick HfO2. However, it was not obtained when the thickness of HfO2 was 10 nm. On the other hand, the MW was observed for Pt/TiN/HfO2 (10 nm)/p-Si(100) diodes utilizing PMA process at 600°C/30 s. The MW was 0.5 V when the bias voltage was applied from -3 to 3 V.

Programmable Metallization Cell (PMC) Random Access Memory is based on the electrochemical growth and removal of nanoscale metallic pathways in thin films of solid electrolytes. In this study, we investigate the nature of thin films formed by the photo doping of Cu into chalcogenide materials for use in programmable metallization cell devices. These devices rely on metal ion transport in the film so produced to create electrically programmable resistance states. The results imply that a Cu-rich phase separates owing to the reaction of Cu with free atoms from chalcogenide materials.

In this letter, we present the new type parallel-coupled band-pass filter (BPF) which uses the dielectric guide in coupled sections with finite metallization thickness. A mode-matching method has been used to analyze this new structure and the simulation results are shown and validated through comparison with other available data. The results in this letter show that the dielectric guide of coupled lines with finite metal strips can be newly added to the design parameters of the parallel-coupled BPF structure and other microwave applications.

A high temperature performance of a W2N compound barrier in the model electrode configuration of W/W2N/poly-Si was examined. The stacked electrode was fairly stable upon annealing at 850 for 1 h. In this electrode configuration, the decomposition and outdiffusion of nitrogen, which were observed in the electrode with a WNx barrier incorporating nitrogen atoms at the interstitial sites in the bcc W lattice, were completely suppressed. We interpreted that the obtained excellent high temperature performance was attributed to the strong chemical interaction forming chemical bonds between nitrogen and W atoms in the W2N compound barrier.

An experimental report was presented on a high temperature performance of a ZrN barrier in the model system of W/ZrN/poly-Si as a poly-metal gate electrode configuration. The absence of interdiffusion, reaction and/or mixing of the ZrN barrier with adjoining W and poly-Si layers resulted in a successful demonstration of the thermally stable poly-metal gate electrode configuration which tolerated annealing at 850 for 1 h.

A 0.25-µm BiCMOS technology has been developed using three sophisticated technologies; the HSST/BiCMOS device, synchrotron orbital radiation (SOR) X-ray lithography, and an advanced two-level metallization. The HSST/BiCMOS provides a 25.4-ps double-poly bipolar device using High-performance Super Self-Aligned Process Technology (HSST), and a 42 ps/2 V CMOS inverter. SOR lithography allows a 0.18 µm gate and 0.2 µm via-hole patternings by using single-level resists. The metallization process features a new planarization technique of the 0.3-µm first wire, and a selective CVD aluminum plug for a 0.25 µm via-hole with contact resistance lower than 1Ω. These 0.25-µm technologies are used to successfully fabricate a 4 KG 0.25 µm CMOS gate-array LSI on a BiCMOS test chip of 12 mm square, which operates at 58 ps/G at 2 V. This result demonstrates that SOR lithography will pave the way for the fabrication of sub-0.25-µm BiCMOS ULSIs.

Via electromigration (EM) performance of aluminum based metallization (AL) systems has been investigated for vias chains of 1500-4000 vias of 1.0 micron diameter. The results show that via EM lifetime can not be enhanced by a simple increase of M2 step coverage in AL/AL vias because the EM induced voids are formed at AL/AL via interface where electrons flow from Ml to M2 even in the case of very poor M2 step coverage. The voids are induced by the boundary layer in AL/AL vias, where a temperature gradient causes discontinuity of aluminum atoms flux. The failure location is not moved though via EM lifetime can be improved by controlling stress in passivation, sputter etch removal thickness and grain size of the first metal. Next, the effect of the boundary layer are eliminated by depositing titanium under the second aluminum or depositing WSi on the first aluminum. In the both cases, via EM lifetime are improved and the failure locations are changed. Especially WSi layer suppresses the voids formation rather than titanium. Models for the failure mechanism in each metallization system are further discussed.