One method for achieving high-speed waveform digitizing uses time-interleaved A-D Converters (ADCs). It is known that, in this method, using multiple ADCs enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique for automatic test equipment applications. This method can be applied to any number of interleaved ADCs, and it does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead.

A new method of cancellation of IM3 using current feedback has been proposed for a multi-stage RFIC amplifier. In order to cancel the IM3 present in an output signal of the amplifier, the IIP3 level and IM3 phase of the amplifier are adjusted by means of feedback circuit techniques, so that the target specification is satisfied. By estimating the IIP3 level and IM3 phase variations for two states in situations with and without feedback possessing linear factors, the parameters of a feedback circuit can be calculated. To confirm the validity of the method, we have investigated two approaches; one including an analytical approach to designing a two-stage feedback amplifier, achieving an IIP3 level improvement of 14.8 dB. The other method involves the fabrication of single-stage amplifiers with and without feedback, operating at 850 MHz, both of which were designed as an integrated circuit using a 0.18 µm SiGe BiCMOS process. The fabricated IC's were tested using a load-pull measurement system, and a good agreement between the estimated and measured IIP3 level and IM3 phase variations has been achieved. Further studies show that the error in these variations, as estimated by the method, has been found to be less than 1.5 dB and 15 degrees, respectively, when the load admittance at 1701 MHz was greater than 1/50 S.

Dynamic non-linearities are of more importance in highly-linear high-speed applications such as software radios. In this paper, a fully-analytical approach to estimate the statistics of dynamic non-linearity parameters of pipeline analog-to-digital converters (ADCs) in the presence of circuit non-idealities is presented. These imperfections include the capacitor mismatches and the non-idealities in the operational amplifiers (op-amps). The most two important ADC dynamic non-linearity parameters, the spurious-free dynamic range (SFDR) and the signal-to-noise-and-distortion ratio (SNDR) are quantified here and closed-form formulas are presented. These formulas are useful for design automation as well as hand calculations of highly-linear pipeline ADCs. Behavioral simulations are presented to show the accuracy of the proposed equations.

A novel optical transmission line consisted of fibers characterized by positive and negative medial dispersion of NZ-DSF and SMF was designed and fabricated. Both P-MDF and N-MDF have achieved the medial dispersion and low non-linearity simultaneously. Total characteristics were confirmed to be suitable for the future high-bit-rate transmission.

The linearity of the GaAs Field Effect Transistor (FET) power amplifier is greatly influenced by the nonlinear characteristics of gate-source capacitance (Cgs) and drain-source current (Ids) for the FETs. However, previously suggested analysis methods of GaAs FET non-linearity are mainly focused on the investigations by each individual non-linear component (Cgs or Ids) without considering both non-linear effects. We analyze more accurately the non-linearity of GaAs FETs by considering non-linear effects of Cgs and Ids simultaneously. We also investigate the third-order intermodulation distortion (IMD3) of the GaAs FET in relation to source and load impedances that minimize FET non-linearities. From the simulation results by Volterra-series technique, we show that the least IMD3 is found at the minimum source resistance (RS) and maximum load resistance (RL) in the equivalent output power (Pout) contour. Simulated results are compared with the load and source pull data, with good agreement.

It is well known that the existence of electrically resistive film layers formed on contact surfaces increases contact resistance and it causes a nonlinear relationship between voltage and current observed in a contact layer. Nonlinear distortion voltages can be detected by our sensitive detection system based on the dual frequency method when a thin film exists on the surface. In this study, multilayer films of polyimide (PI) was used as an ideal material of ultra thin film, because of electrically good insulator with simple molecular structure, to study non-linearity through metal-insulator-metal contact. The number of deposited layers between one and twenty one were formed on three types of substrates; (a) evaporated gold on a glass plate, (b) gold plate and (c) evaporated gold on gold plate, to obtain good insulating film. Where each layer of PI film has 0. 4 nanometer thickness. A pin contact was made by pressing a bent gold wire on the PI film. It is concluded that [1]; the second-order distortion voltage increases exponentially as the film thickness increases, [2]; polarity of the surface potential of PI depends on the film thickness, and that I-V characteristic depends on the polarity of the surface potential.