This paper develops a design method and theoretical analysis for piecewise nonlinear oscillators that have desired circular limit cycles. Especially, the mathematical proof on existence, uniqueness, and stability of the limit cycle is shown for the piecewise nonlinear oscillator. In addition, the relationship between parameters in the oscillator and rotational directions and periods of the limit cycle trajectories is investigated. Then, some numerical simulations show that the piecewise nonlinear oscillator has a unique and stable limit cycle and the properties on rotational directions and periods hold.

We present on-chip oscillator arrays synchronized by random noises, aiming at skew-free clock distribution on synchronous digital systems. Nakao et al. recently reported that independent neural oscillators can be synchronized by applying temporal random impulses to the oscillators [1],[2]. We regard neural oscillators as independent clock sources on LSIs; i.e., clock sources are distributed on LSIs, and they are forced to synchronize through the use of random noises. We designed neuron-based clock generators operating at sub-RF region (< 1 GHz) by modifying the original neuron model to a new model that is suitable for CMOS implementation with 0.25-µm CMOS parameters. Through circuit simulations, we demonstrate that i) the clock generators are certainly synchronized by pseudo-random noises and ii) clock generators exhibited phase-locked oscillations even if they had small device mismatches.