In this paper, a hardware efficient design methodology for a configurable-point multiple-stream pipeline FFT processor is presented. We first compared the memory and arithmetic components of different pipeline FFT architectures, and obtained the conclusion that MDF architecture is more hardware efficient than MDC for the overall processor. Then, in order to reduce the computational complexity, a binary-tree representation was adopted to analyze the decomposition algorithm. Consequently, the coefficient multiplications are minimized among all the decomposition probabilities. In addition, an efficient output reorder circuit was designed for the multiple-stream architecture. An 128∼2048 point 4-stream FFT processor in LTE system was designed in SMIC 55nm technology for evaluation. It owns 1.09mm2 core area with 82.6mW power consumption at 122.88MHz clock frequency.

We present area- and power-efficient pipeline 128- and 128/64-point fast Fourier transform (FFT) processors for 8x8 multiple-input multiple-output orthogonal frequency multiplexing (MIMO-OFDM) systems based on the specification framework of IEEE 802.11ac WLANs. Our new FFT processors use mixed-radix multipath delay commutator (MRMDC) architecture from the point of view of low complexity and high memory use. A conventional MRMDC architecture induces large circuits in delay commutators, which change the order of data sequences for the butterfly units. The proposed architecture replaces delay elements with new commutators that cooperate with other MIMO-OFDM processing blocks. These commutators are inserted in the front and rear of the input and output memory units. Our FFT processors exhibit a 50–51% reduction in logic gates and 70–72% reduction in power dissipation as compared with conventional ones.

A time-domain equalization (TEQ) algorithm is presented to shorten the effective channel impulse response to increase the transmission efficiency of the 54 Mbps IEEE 802.11a orthogonal frequency division multiplexing (OFDM) system. In solving the linear equation Aw = B for the optimum TEQ coefficients, A is shown to be Hermitian and positive definite. The LDLT and LU decompositions are used to factorize A to reduce the computational complexity. Simulation results show high performance gains at a data rate of 54 Mbps with moderate orders of TEQ finite impulse response (FIR) filter. The design and implementation of the algorithm in field programmable gate array (FPGA) are also presented. The regularities among the elements of A are exploited to reduce hardware complexity. The LDLT and LU decompositions are combined in hardware design to find the TEQ coefficients in less than 4 µs. To compensate the effective channel impulse response, a radix-4 pipeline fast Fourier transform (FFT) is implemented in performing zero forcing equalization. The hardware implementation information is provided and simulation results are compared to mathematical values to verify the functionalities of the chips running at 54 Mbps.