We propose hardware-aware sum-product (SP) decoding for low-density parity-check codes. To simplify an implementation using a fixed-point number representation, we transform SP decoding in the logarithm domain to that in the decision domain. A polynomial approximation is proposed to implement an update rule of the proposed SP decoding efficiently. Numerical simulations show that the approximate SP decoding achieves almost the same performance as the exact SP decoding when an appropriate degree in the polynomial approximation is used, that it improves the convergence properties of SP and normalized min-sum decoding in the high signal-to-noise ratio regime, and that it is robust against quantization errors.

A novel real-time solar photovoltaic (SPV) emulator system, based on a systolic array network (SAN), is presented. This architecture follows the piecewise polynomial approximation and parallel computing techniques, and shows its capability to generate high-accuracy I-V, P-V curves, instead of traditional DSP and lookup table-based SPV systems.

Many scientific applications require efficient variable-precision floating-point arithmetic. This paper presents a special-purpose Very Large Instruction Word (VLIW) architecture for variable precision floating-point arithmetic (VV-Processor) on FPGA. The proposed processor uses a unified hardware structure, equipped with multiple custom variable-precision arithmetic units, to implement various variable-precision algebraic and transcendental functions. The performance is improved through the explicitly parallel technology of VLIW instruction and by dynamically varying the precision of intermediate computation. We take division and exponential function as examples to illustrate the design of variable-precision elementary algorithms in VV-Processor. Finally, we create a prototype of VV-Processor unit on a Xilinx XC6VLX760-2FF1760 FPGA chip. The experimental results show that one VV-Processor unit, running at 253 MHz, outperforms the approach of a software-based library running on an Intel Core i3 530 CPU at 2.93 GHz by a factor of 5X-37X for basic variable-precision arithmetic operations and elementary functions.

In this paper, we propose a coding method for camera raw images with high dynamic ranges. Our encoder has two layers. In the first layer, 24 bit low dynamic range image is encoded by a conventional codec, and then the residual image that represents the difference between the raw image and its approximation is encoded in the second layer. The approximation is derived by a polynomial fitting. The main advantage of this approach is that applying the polynomial model reduces the correlation between the raw and 24 bit images, which increases coding efficiency. Experiments shows compression efficiency is significantly improved by taking an inverse tone mapping into account.

Numerical function generators (NFGs) realize arithmetic functions, such as ex,sin(πx), and , in hardware. They are used in applications where high-speed is essential, such as in digital signal or graphics applications. We introduce the edge-valued binary decision diagram (EVBDD) as a means of reducing the delay and memory requirements in NFGs. We also introduce a recursive segmentation algorithm, which divides the domain of the function to be realized into segments, where the given function is realized as a polynomial. This design reduces the size of the multiplier needed and thus reduces delay. It is also shown that an adder can be replaced by a set of 2-input AND gates, further reducing delay. We compare our results to NFGs designed with multi-terminal BDDs (MTBDDs). We show that EVBDDs yield a design that has, on the average, only 39% of the memory and 58% of the delay of NFGs designed using MTBDDs.

The current letter extends narrow band (NB) local polynomial approximation (LPA) beamforming to wide band (WB) rapidly moving sources. Instead of the conventional beamformer weight in NB LPA, the proposed method adopts the steered minimum variance (STMV) method that can achieve a high resolution with short time observations. The performance of the proposed algorithm is demonstrated via computer simulations.

We frequently use a polynomial to approximate a complex function. This study shows a method which determines the optimum coefficients and the number of terms of the polynomial, and the error of the polynomial is estimated.

In this letter, we propose a blind adaptive receiver with nonlinear structure for DS/CDMA communication systems. The proposed receiver requires the signature waveform and timing for only the desired user. It is shown that the blind adaptation is equivalent to the adaptation with the training signal and the function to be minimized has no local minima.