This paper discusses the resilience of networks based on graph theory and stochastic process. The electric power network where edges may fail simultaneously and the performance of the network is measured by the ratio of connected nodes is supposed for the target network. For the restoration, under the constraint that the resources are limited, the failed edges are repaired one by one, and the order of the repair for several failed edges is determined with the priority to the edge that the amount of increasing system performance is the largest after the completion of repair. Two types of resilience are discussed, one is resilience in the recovery stage according to the conventional definition of resilience and the other is steady state operational resilience considering the long-term operation in which the network state changes stochastically. The second represents a comprehensive capacity of resilience for a system and is analytically derived by Markov analysis. We assume that the large-scale disruption occurs due to the simultaneous failure of edges caused by the common cause failures in the analysis. Marshall-Olkin type shock model and α factor method are incorporated to model the common cause failures. Then two resilience measures, “operational resilience” and “operational resilience in recovery stage” are proposed. We also propose approximation methods to obtain these two operational resilience measures for complex networks.

In a power network, it is important to detect a cyber attack. In this paper, we propose a method for detecting false data injection (FDI) attacks in distributed state estimation. An FDI attack is well known as one of the typical cyber attacks in a power network. As a method of FDI attack detection, we consider calculating the residual (i.e., the difference between the observed and estimated values). In the proposed detection method, the tentative residual (estimated error) in ADMM (Alternating Direction Method of Multipliers), which is one of the powerful methods in distributed optimization, is applied. First, the effect of an FDI attack is analyzed. Next, based on the analysis result, a detection parameter is introduced based on the residual. A detection method using this parameter is then proposed. Finally, the proposed method is demonstrated through a numerical example on the IEEE 14-bus system.

In the state estimation of steady-state power networks, a cyber attack that cannot be detected from the residual (i.e., the estimation error) is called a false data injection (FDI) attack. In this letter, to enforce the security of power networks, we propose a method of detecting an FDI attack. In the proposed method, an FDI attack is detected by randomly choosing sensors used in the state estimation. The effectiveness of the proposed method is presented by two examples including the IEEE 14-bus system.

In this paper, the Multi-voltage (multi-Vdd) variable pipeline router is proposed to reduce the power consumption of Network-on-Chips (NoCs) designed for Chip Multi-processors (CMPs). The multi-Vdd variable pipeline router adjusts its pipeline depth (i.e., communication latency) and supply voltage level in response to the applied workload. Unlike Dynamic Voltage and Frequency Scaling (DVFS) routers, the operating frequency remains the same for all routers throughout the CMP; thus, omitting the need to synchronize neighboring routers working at different frequencies. Two types of router architectures are presented: a Coarse-Grained Variable Pipeline (CG-VP) router that changes the voltage supplied to the entire router, and a Fine-Grained Variable Pipeline (FG-VP) router that uses a finer power partition. The evaluation results showed that the CG-VP and FG-VP routers achieve a 22.9% and 35.3% power reduction on average with 14% and 23% area overhead in comparison with a baseline router without variable pipelines, respectively. Thanks to the adopted look-ahead mechanism to switch the supply voltage, the performance overhead is only 4.4%.

Silicon photonics Network-on-Chips (NoCs) have emerged as an attractive solution to alleviate the high power consumption of traditional electronic interconnects. In this paper, we propose a fully optical ring NoC that combines static and dynamic wavelength allocation communication mechanisms. A different wavelength-channel is statically allocated to each destination node for light weight communication. Contention of simultaneous communication requests from multiple source nodes to the destination is solved by a token based arbitration for the particular wavelength-channel. For heavy load communication, a multiwavelength-channel is available by requesting it in execution time from source node to a special node that manages dynamic allocation of the shared multiwavelength-channel among all nodes. We combine these static and dynamic communication mechanisms in a same network that introduces selection techniques based on message size and congestion information. Using a photonic NoC simulator based on Phoenixsim, we evaluate our architecture under uniform random, neighbor, and hotspot traffic patterns. Simulation results show that our proposed fully optical ring NoC presents a good performance by utilizing adequate static and dynamic channels based on the selection techniques. We also show that our architecture can reduce by more than half, the energy consumption necessary for arbitration compared to hybrid photonic ring and mesh NoCs. A comparison with several previous works in term of architecture hardware cost shows that our architecture can be an attractive cost-performance efficient interconnection infrastructure for future SoCs and CMPs.

In this paper, an efficient method is proposed to accurately analyze large-scale power/ground (P/G) networks, where inductive parasitics are modeled with the partial reluctance. The method is based on frequency-domain circuit analysis and the technique of vector fitting, and obtains the time-domain voltage response at given P/G nodes. The frequency-domain circuit equation including partial reluctances is derived, and then solved with the GMRES algorithm with rescaling, preconditioning and recycling techniques. With the merit of sparsified reluctance matrix and iterative solving techniques for the frequency-domain circuit equations, the proposed method is able to handle large-scale P/G networks with complete inductive modeling. Numerical results show that the proposed method is orders of magnitude faster than HSPICE, several times faster than INDUCTWISE, and capable of handling the inductive P/G structures with more than 100,000 wire segments.

Next generation advanced power devices show remarkable progress in wide band-gap power devices such as silicon carbide and gallium nitride devices, as well as novel silicon devices called as super junction FETs and so on. The future direction of power electronics applications is surveyed in terms of output power density as an index of future power electronics development, instead of the power conversion efficiency, taking the device progress in sight. Over the last 30 years, the output power density of power electronics apparatuses has increased by a factor of two figures. New markets, such as a power supply for future generation CPU, a compact unit inverter and a electric vehicle-driving inverter unit, are expected to grow rapidly from 2010 to 2015 with the advance in the out power density of power converter. The possibility of power electronics innovation with progress in the output power density will be discussed in conjunction with development of next generation advanced power devices and related technologies.