A time-slicing ring oscillator (TSRO) which captures time-dependent delay degradation due to periodic transient voltage drop on a power supply network is proposed. An impact of the supply voltage fluctuations, including voltage drop and overshoot, on logic circuit delay is evaluated as a change of oscillation frequency. The TSRO is designed using standard logic cells so that it can be placed almost anywhere in a digital circuit wherein supply voltage fluctuation is concerned. We also propose a new procedure for reconstructing supply voltage waveform. The procedure enables us to accurately monitor time-dependent, effective supply voltages. The -1 dB bandwidth of the TSRO is simulated to be 15.7 GHz, and measured time resolution is 131 ps. Measurement results of a test chip using 90-nm standard CMOS process successfully proved the feasibility of both delay degradation and effective supply voltage fluctuation measurements. Measurement of spatial voltage drop fluctuation is achieved.

A novel voltage measurement circuit which utilizes process variation is proposed. Using the proposed circuit, the voltage of a nonperiodic waveform at a particular time point can be accurately captured by a single clock pulse (one-shot measurement). The proposed circuit can be designed without compensation circuits against process variation, and thus occupies only a small area. An analytical expression of offset voltage for the comparator utilizing process variation (UPV-comparator), which plays a key role in the proposed circuit, is derived and design considerations for the proposed circuit are discussed. The circuit operation is confirmed through SPICE simulation using 90 nm CMOS device models. The -0.04 and -3 dB bandwidths (99% and 50% amplitudes) of the proposed circuit are about 10 MHz and far over 1 GHz, respectively. The circuit area is also estimated using an experimental layout.