In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitance. The methodology was validated by designing several MCML circuits in an IBM 130 nm CMOS process.

An efficient way to optimize the hardware consumption in a low-voltage ΔΣ modulator for D/A converters is described. The modulator employs a ROM selection scheme for multiplications and the new buffer-and-routing ROM structure to minimize the hardware consumption. Furthermore, a guideline of the power-delay-and-area product (PDAP) for compelling issues such as power dissipation, delay time, and chip area consumption in the modern digital-circuit design is proposed. After the validity of the concept has been proved in comparison with that of the conventional guideline of the power-delay product in several behavioral blocks, it was employed in the circuit design. Fabricated in a standard digital 0.35-µm CMOS technology, the modulator achieves a signal-to-noise ratio (SNR) of 96 dB with an oversampling ratio of 256 under the supply of 2.0 V.

Decreased power dissipation and transient voltage drops in CMOS power distribution networks are important for high-speed deep submicrometer CMOS integrated circuits. In this paper, three CMOS buffers based on the charge-transfer, split-path and bootstrapped techniques to reduce the power dissipation and transient voltage drop in power supply are proposed. First, the inverted-delay-unit is used in the low-power inverted-delay-unit (LPID) CMOS buffer to eliminate the short-circuit current of the output stage. Second, the low-swing bootstrapped feedback-controlled split-path (LBFS) CMOS buffer is proposed to eliminate the short-circuit current of the output stage by using the feedback-controlled split-path method. The dynamic power dissipation of the LBFS CMOS buffer can be reduced by limiting the gate voltage swing of the output stage. Moreover, the propagation delay of the LBFS CMOS buffer is also reduced by non-full-swing gate voltage of the output stage. Third, the charge-recovery scheme is used in the charge-transfer feedback-controlled 4-split-path (CRFS) CMOS buffer to recovery and pull up the gate voltage of the output stage for reducing power-delay product and power line noise. Based on HSPICE simulation results, the power-delay product and the transient voltage drop in power supply of the proposed three CMOS buffers can be reduced by 20% to 40% as compared to conventional CMOS tapered buffer under various capacitive load.

This paper surveys low-power circuit techniques for CMOS ULSIs. For many years a power supply voltage of 5 V was employed. During this period power dissipation of CMOS ICs as a whole increased four-fold every three years. It is predicted that by the year 2000 the power dissipation of high-end ICs will exceed the practical limits of ceramic packages, even if the supply voltage can be feasibly reduced. CMOS ULSIs now face a power dissipation crisis. A new philosophy of circuit design is required. The power dissipation can be minimized by reducing: 1) supply voltage, 2) load capacitance, or 3) switching activity. Reducing the supply voltage brings a quadratic improvement in power dissipation. This simple solution, however, comes at a cost in processing speed. We investigate the proposed methods of compensating for the increased delay at low voltage. Reducing the load capacitance is the principal area of interest because it contributes to the improvement of both power dissipation and circuit speed. Pass-transistor logic is attracting attention as it requires fewer transistors and exhibits less stray capacitance than conventional CMOS static cicuits. Variations in its circuit topology as well as a logic synthesis method are presented and studied. A great deal of research effort has been directed towards studying every portion of LSI circuits. The research achievements are categorized in this paper by parameters associated with the source of CMOS power dissipation and power use in a chip.