The application of network function virtualization (NFV) and software-defined networking (SDN) to passive optical networks (PONs) is attracting attention for the deployment of cost-effective access network systems. This paper presents a novel architecture of a programmable finite state machine (P-FSM) as a hardware accelerator for protocol processing in an optical line terminal (OLT). The P-FSM is programmable hardware that manages various types of FSMs to enhance flexibility in OLTs and achieve wired-rate performance with a negligible increase in total chip area. The P-FSM is implemented using three key technologies: a specific architecture for state management of communications protocols to minimize the logic area, a memory distributed implementation to minimize the program memory, and a new branch operation to minimize the memory area and reduce processing time. Evaluation results show that the P-FSM can handle 10G-EPON/NG-PON2 communications protocols in the same architecture while achieving wired-rate performance. The increase in the total designed area is only 1.5% to 4.9% depending on the number of protocols supported compared to the area of a conventional communications SoC without flexibility. We also clarify that our architecture has the scalability needed to modify the number of FSMs and the maximum number of ONU connections according to the system scale.

This paper proposes a new processor architecture for manipulating the protocols of digital signal transport systems. In order to offer various kinds of telecommunication services, flexibility as well as high performance is required of digital signal transport systems. To realize such systems, this architecture consists of a core CPU, memories, and dedicated application-specific hardware. Software on the core CPU offers flexibility, while the dedicated hardware provides performance. A computer simulation confirms the efficiency of the architecture.

This paper proposes polling-based real-time software for MPEG2 System protocol LSIs, which is a typical embedded and real-time system on a chip, and demonstrates its performance and usefulness. The polling-based real-time software is designed and optimized by analyzing application specific function requirements and deciding scheduling intervals and the execution cycles of each task. It requires neither hardware for multiple interrupt handling nor software for heavy context switching. The polling-based approach provides sufficient performance without any hardware and software overhead for a real-time application like the MPEG2 System protocol.

Three techniques are proposed for reducing the time required for protocol processing: protocol data unit management using page management, assembly and disassembly of data packet header and contents in hardware, and rescheduling of protocol processing. These techniques were shown to be feasible by applying them to the TCP/IP over a fiber-distributed data interface network. The maximum communication throughput was 91.6 Mbps; the total throughput for 64 sessions was 89.6 Mbps, only 2% less than the maximum. These techniques will enable the development of more effcient video-on -demand systems.

Recently actual use of the OSI standardized protocols has begun on client-server systems of LANs, and reduction of OSI protocol overheads in high-speed networks has become more important. We studied a parallel-processing architecture for Message Handling System (MHS), which requires a large amount of protocol processing and is expected to be used widely. We implemented a prototype MHS server with performance scalable to number of CPUs, by porting an existing MHS software with minimum modification. This paper reports on the parallel processing scheme, hardware and software architecture of the prototype, as well as evaluation of the scheme based on measurement and simulation.