We consider a finite-capacity single-server queue with constant service and vacation times, which is seen in the time division multiple access (TDMA) scheme. First we derive the probability that j customers remain in the queue when a test customer arrives. Using this probability we then evaluate the probability that the test customer who arrives during the vacation or service time has to wait in the queue for longer than a given time. From these results, we obtain the waiting time distribution for the customer arriving at an arbitrary time. We also show a practical application to wireless TDMA communications systems.

CDMA unslotted ALOHA system with finite size of queueing buffers is discussed in this paper. We introduce an analytical model in which the system is divided into two Markov chains; one is in the user part, and the other is in the channel part. In the user part, we can model the queueing behavior of the user station as an M/G/1/B queue. In the channel part, we can consider the number of simultaneously transmitted packets as an M1 + M2/D///K queue. We analyze the queueing system by using this analytical model, and evaluate the effect of buffer capacity in terms of the throughput, the rejection probability and the average delay. As a result, increase in the buffer size brings about an improvement in the grade of service in terms of higher throughput and lower rejection probability.

Many `output-scheduling' algorithms have been proposed for improving the performance of input queueing asynchronous transfer mode (ATM) switches, whereby cells from different random-access input queues destined for the same output can be scheduled for non-conflicting transmissions. An optimal output-scheduling algorithm, one with the full coordination of transmissions to all outputs, can approach the performance of output queueing. Because of the complexity of such an optimal scheduler, output schedulers proposed in the literature are without such coordination. We propose a simple way to incorporate such a full coordination in output-scheduling with much simple hardware, for small size switches. Throughput of the input queueing switch thus approaches that of the output queueing switch, without speed-up, input/output grouping or complicated hardware. To make the output-scheduling algorithm fast enough, we incorporate parallelism and pipelining. We perform detailed simulation study of the performance of the input queueing switch with the proposed scheduling algorithm.

This paper introduces and studies the performance of an NN space-division, single-stage ATM switch with dual input-queueing. Each input port has two separate FIFO queues, an "odd" and an "even" queue. An incoming cell is stored at the input at either of two FIFOs according its output port destination (output ports are also labeled as "odd" or "even"). Hence we call this scheme the Odd-Even switch. We compare the Odd-Even switch to the ordinary input-buffered switch and we find that it can achieve a remarkably higher performance, in terms of throughput, mean delay and cell loss. This is due to the fact that the Head-of-Line effect becomes less problematic under the Odd-Even switch. Our results are based on various traffic models. Finally, we compare the Odd-Even scheme to the Look-ahead (input "window") policy.

Per-Virtual Connection (VC) queueing allows an ATM switch to schedule cells to be transmitted on a link based on their VC. This alternative to the traditional First-In-First-Out(FIFO)queueing, in which cells from different VCs of the same priority are stored in a common queue, is implemented by some switch manufacturers. This paper assesses the merits of per-VC scheduling in regards to capacity, traffic shaping, and interworking with traffic management mechanisms such as connection admission control (CAC) and use of queue thresholds. The paper also discusses the conditions which favor the use of per-VC scheduling.

We analyze M,MMPP/G/1 finite queues with queue-length-threshold (QLT) scheduling policy and Bernoulli schedule where the arrival of type-1 customers (nonreal-time traffic) is Poisson and the arrival of type-2 customers (real-time traffic) is a Markov-modulated Poisson process (MMPP). The next customer to be served is determined by the queue length in the buffer of type-1 customers. We obtain the joint queue length distribution for customers of both types at departure epochs by using the embedded Markov chain method, and then obtain the queue length distribution at an arbitrary time by using the supplementary variable method. From these results, we obtain the loss probabilities and the mean waiting times for customers of each type. The numerical examples show the effects of the QLT scheduling policy on performance measures of the nonreal-time traffic and the bursty real-time traffic in ATM networks.

In this Letter, we investigate the loss performance of a discrete-time single-server queueing system with periodic vacations, with which we are often confronted in traffic control, such as cell scheduling or priority control schemes, at ATM nodes. Explicit expressions are derived for the cell loss ratio in terms of the distribution of the buffer contents in an infinite capacity queue.

We investigate an importance sampling (IS) simulation of MMPP/D/1 queueing to obtain an estimate for the survivor function P(Q > q) of the queue length Q in the steady state. In Ref.[11], we studied the IS simulation of 2-state MMPP/D/1 queueing and obtained the optimal simulation distribution, but the mathematical fundation of the theory was not enough. In this paper, we construct a discrete time Markov chain model of the n-state MMPP/D/1 queueing and extend the results of Ref.[11] to the n-state MMPP/D/1. Based on the Markov chain model, we determine the optimal IS simulation distribution fo the n-state MMPP/D/1 queueing by applying the large deviations theory, especially, the sample path large deviations theory. Then, we carry out IS simulation with the obtained optimal simulation distribution. Finally, we compare the simulation results of the IS simulation with the ordinary Monte Carlo (MC) simulation. We show that, in a typical case, the ratio of the computation time of the IS simulation to that of the MC simulation is about 10-7, and the 95% confidence interval of the IS is slightly improved compared with the MC.

To implement the PGPS packet scheduling algorithm in high speed networks is more difficult since it is based on real time simulation of an equivalent fluid-model system leading to a higher implementation time complexity. A modified approach to PGPS is the SCFQ scheme. This scheme is easy to implement, but has an increasing end-to-end delay bound. The VC packet scheduling algorithm provides the same end-to-end delay bound as PGPS does, but has the disadvantage of unfairness. As SCFQ, SFQ is much easier to implement than PGPS and achieves the same fairness, but has a higher end-to-end delay bound than PGPS. We propose a new packet scheduling algorithm, called Minimum Starting-tag Fair Queueing (MSFQ), which assigns the virtual time to be the minimum starting tag over all backlogged connections. MSFQ is much easier to implement than PGPS and provides the same end-to-end delay bound for each connection and fairness as PGPS. In this paper, we will show the end-to-end delay bound and fairness of MSFQ and compare 5 rate-based packet scheduling algorithms including PGPS, VC, SCFQ, SFQ, and MSFQ focusing on end-to-end delay bound, fairness, and implementation time complexity.

In this paper, we propose a new switching network architecture with output queueing, The proposed switch, FBSF (FAB Banyan Switching Fabrics) can deliver up to 2r packets simultaneously destined for the same outlet in a single time slot. The switch fabrics consist of Batcher sorter, a radix-r double shuffle network r-packet distributors, two FAB networks, and output buffer modules. The performance of the switch fabric is evaluated by measures of throughput, average queue length, average waiting time, and packet loss rate. Numerical and simulation results indicate that the switch exhibits very good delay-throughput performance over a wide range of input traffic.

Multipath interconnection networks can support higher bandwidth than those of nonblocking networks by passing multiple packets to the same output simultaneously and these packets are buffered in the output buffer. The delay-throughput performance of the output buffer in multipath networks is closely related to output traffic distribution, packet arrival process at each output link connected to a given output buffer. The output traffic distributions are different according to the various input traffic patterns. Focusing on nonuniform output traffic distributions, this paper develops a new, general analytic model of the output buffer in multipath networks, which enables us to investigate the delay-throughput performance of the output buffer under various input traffic patterns. This paper also introduces Multipath Crossbar network as a representative multipath network which is the base architecture of our analysis. It is shown that the output buffer performances such as packet loss probability and delay improve as nonuniformity of the output traffic distribution becomes larger.

A connection admission control (CAC) that guarantees a negotiated cell-loss ratio for all cell-streams passing through the usage parameter control (UPC) in ATM networks is proposed. In particular, the cases in which a jumping-window, sliding-window, or continuous-leaky-bucket scheme are used for peak-cell-rate policing are discussued, and the upper bound for cell-loss ratio of the cell-streams passing through each type of UPC is derived. The CACs based on the derived cell-loss-ratio upper bounds ensure the quality of service in all cases by combining the relevant UPCs. There are three possible combinations of CAC and UPC, depending on the UPC mechanism used. The impact of the choice of CAC and UPC combination on bandwidth utilization is discussed using several numerical examples.

The emerging, ATM network will support permanent, semi-permanent and switched virtual channel connections (SVCC). A number of simulation studies have been carried out to study the performance of SVCCs using empirical data. The absence of an analytical model has prevented the study of SVCCs under known traffic distributions. In this paper, we develop a new delayed vacation model to facilitate the performance study of SVCCs with configurable inactivity timer in the ATM network interface card (NIC). Comparison with simulation results indicates that the proposed model is very accurate and can be effectively used to optimise the performance of SVCCs by selecting an appropriate inactivity timer.

In this paper, we evaluated performance of mobile exchange control network. Queueing network model is used for modeling of mobile exchange control network. We developed a call control processing and location registration scenario that has a message exchange function between processors in mobile exchange control network. The network symbols are used the simulation models that are composed of the initialization module, message generation module, message routing module, message processing module, message generation module, HIPC network processing module, output analysis module. As a result of computer simulation, we obtain the processor utilization, the mean queue length, the mean waiting time of control network based on call processing and location registration capacity. The call processing and location registration capacity are referred by the number of call attempts in the mobile exchange and must be satisfied with the quality of service (delay time).

This paper provides a queueing model analysis of virtual route networks for which a pacing window flow control mechanism is employed with an input queue included. The input queue is introduced into the model to describe the waiting system where messages prevented from entering the network are stored in first-come first-serve manner. Both cases of finite and infinite capacity are considered. The model leads to a Markovian queueing system, which is fully solved through appropriate use of matrix-geometric methods. The empirical rule is that the optimum window size which maximizes the power criterion including the admission delay is nearly twice the number of hops (nodes of the network). Simulations are presented to verify the analytical results. Finally, performance comparisons with the sliding window protocol are made. Our results show that although the average number of messages in the network is higher for the pacing window case, when the input queue delay is taken into consideration the overall performance of the pacing window protocol is better than that of the sliding window.

A new ATM switch architecture, named shared multibuffering, features great advantages on memory access speed for a large switch, and overall size of buffer memories to achieve excellent cell-loss performance. We have developed a 622-Mb/s 88 shared multibuffer ATM switch with multicast functions and hierarchical queueing functions to accommodate 156-Mb/s, 622-Mb/s and 2.4-Gb/s interfaces. Implementation of the shared multibuffer ATM switch is described with respect to the four sorts of 0.8-µm BiCMOS LSIs and ATM switch boards. The switch board/type-1, with C1-LSI, allows to accommodate effectively 156-Mb/s and 622-Mb/s interfaces, which is suitable for an ATM access system. The switch board/type-2, with C2-LSI, can provide multicast functions and accommodate a 2.4-Gb/s interface. By using four switch boards, it is possible to apply them to a 2.4-Gb/s ATM loop system.

This paper concerns optimized facility design for VLSI production. The methods proposed are applicable in planning LSI production facilities with a good balance between the number of machines and the number of operators. The sequence in each processing step is analyzed in detail. A new algorithm based on the queueing model is developed for estimating the simultaneous requirements for the two kinds of resources, machines and operators. This estimation system can be applied to complicated fabrication schemes, such as batch processing, continuous processing, and mixed technologies. This methodology yields guidelines for ASIC LSI production system design.

G/D/1 is a theoretic model for ATM network queueing based on processing cells. We investigate the G/D/1 system by discrete time modeling. Takacs' combinatorial methods are applied to analyze the system performance. An approximation for the survivor function P[Q > q], which is the probability that the queue length Q in the stationary state exceeds q, is obtained. The obtained formula requires only very small computational complexity and gives good approximation for the true value of P[Q > q].

We study behavior of multi-zone MCA (Multi-Channel Access) mobile communication systems with a finite number of channels in each zone. Three queueing schemes for channel requests named holding scheme, ready-nonready scheme, and optimum scheme are investigated. The delay performance of channel requests is studied through computer simulations.

Over the last decade, the Internet has been extremely successful by distinguishing between overlaying applications and underlying networking technologies. This approach allows rapid and independent improvement in both networking and application technologies. The internetworking layer that divides applications and the network enables the Internet to function as a general and evolving infrastructures for data communications. The current Internet architecture offers only best-effort data delivery. However, recent emerging computer and networking technologies, demand the Internet guaranteed performance. In particular, audio and video applications have more rigid delay requirement than those applications which the current Internet supports. To offer guaranteed services in addition to best-effort services, both a new service model and a new architecture are necessary in the Internet architecture. The paper surveys researches and experiments conducted in the Internet community to accommodate a wide variety of qualities of services.