Linear feed-forward/feedback shift registers are used as an effective tool of testing circuits in various fields including built-in self-test and secure scan design. In this paper, we consider the issue of testing linear feed-forward/feedback shift registers themselves. To test linear feed-forward/feedback shift registers, it is necessary to generate a test sequence for each register. We first present an experimental result such that a commercial ATPG (automatic test pattern generator) cannot always generate a test sequence with high fault coverage even for 64-stage linear feed-forward/feedback shift registers. We then show that there exists a universal test sequence with 100% of fault coverage for the class of linear feed-forward/feedback shift registers so that no test generation is required, i.e., the cost of test generation is zero. We prove the existence theorem of universal test sequences for the class of linear feed-forward/feedback shift registers.

A generalized version of sequential logic circuit based neuron models is presented, where the dynamics of the model is modeled by an asynchronous cellular automaton. Thanks to the generalizations in this paper, the model can exhibit various neuron-like waveforms of the membrane potential in response to excitatory and inhibitory stimulus. Also, the model can reproduce four groups of biological and model neurons, which are classified based on existence of bistability and subthreshold oscillations, as well as their underlying bifurcations mechanisms.

An asynchronous sequential logic spiking neuron is an artificial neuron model that can exhibit various bifurcations and nonlinear responses to stimulation inputs. In this paper, a pulse-coupled system of the asynchronous sequential logic spiking neurons is presented. Numerical simulations show that the coupled system can exhibit various lockings and related nonlinear responses. Then, theoretical sufficient parameter conditions for existence of typical lockings are provided. Usefulness of the parameter conditions is validated by comparing with the numerical simulation results as well as field programmable gate array experiment results.

A fine-grain bit-serial multiple-valued reconfigurable VLSI based on logic-in-control architecture is proposed for effective use of the hardware resources. In logic-in-control architecture, the control circuits can be merged with the arithmetic/logic circuits, where the control and arithmetic/logic circuits are constructed by using one or multiple logic blocks. To implement the control circuit, only one state in a state transition diagram is allocated to one logic block, which leads to reduction of the complexity of interconnections between logic blocks. The fine-grain logic block is implemented based on multiple-valued current-mode circuit technology. In the fine-grain logic block, an arbitrary 3-variable binary function can be programmed by using one multiplexer and two universal literal circuits. Three-variable binary functions are used to implement the control circuit. Moreover, the hardware resources can be utilized to construct a bit-serial adder, because full-adder sum and carry can be realized by programming in the universal literal circuit. Therefore, the logic block can be effectively reconfigured for arithmetic/logic and control circuits. It is made clear that the hardware complexity of the control circuit in the proposed reconfigurable VLSI can be reduced in comparison with that of the control circuit based on a typically sequential circuit in the conventional FPGA and the fine-grain field-programmable VLSI reported until now.