This paper describes a newly developed FET Coupled Logic (FCL) circuit that operates at very high frequencies with very low supply voltages below 3.3 V. An FCL circuit consists of NMOS source-coupled transistor pairs for current switches, load resistors, emitter followers and current sources that are controlled by a band-gap reference bias generator. The characteristics and performance are discussed by comparing this circuit with other high-speed circuits. The optimal circuit parameters for FCL circuits are also discussed, and the fact is noted that a larger swing voltage enhances the circuit's performance. The simulated delay of a 0.25 µm FCL circuit is less than 15 ps for a 2.5 V power supply, and the simulated maximum toggle frequencies are over 5 GHz and 10 GHz at 2.5 V and 3.3 V power supply, respectively. The simulation results show that FCL circuits achieve the best performance among the current mode circuits, which include ECL circuits, NMOS source-coupled logic circuits. The delay of the FCL circuit is less than half that of an ECL circuit. The maximum toggle frequency of the FCL circuit is about triple that of NMOS source-coupled logic circuit. Because the FCL circuit uses low-cost CMOS-based BiCMOS technologies, its cost performance is superior to ECL circuits that require expensive base-emitter self-aligned processes and trench isolation processes. Using depletion-mode NMOS transistors for current switches can lower the minimum supply voltage for FCL circuits and it is below 1.5 V. The FCL circuit is a promising logic gate circuit for multi-Gbit/s tele/data communication LSIs.

Memory Sharing Processor Array (MSPA) architecture has been developed as an effective array processing architecture for both reduced data storages and increased processor cell utilization efficiency [1]. In this paper, the MSPA design methodology is extended to the VLSI synthesis of a serial input processor array (Pa). Then, a new bit-serial input multiplier and a new data serial input matrix multiplier are derived from the new PA. These multipliers are superior to the conventional multipliers by their smaller number of logic-gate count.

This paper describes a 0.8-µm CMOS LSI developed for a 156-Mb/s serial interface in ATM switching systems. Recently, there have been increasing problems of connector pin neck and higher power consumption when enhancing switching system capacity. To overcome these problems, we have developed an LSI with a high-speed interface by using CMOS technology to achieve low power consumption. A low-swing differential signal level is used to achieve 156-Mb/s data transmission. We named this new circuit technique ALTS (Advanced Low-level Transmission circuit System). Using the LSI, transmission can be achieved between boards or racks through a 10-meter twisted pair cable. The LSI has a 156-Mb/s transmitter-receiver, a serial-to-parallel converter and a parallel-to-serial converter. It performs 19.5-Mb/s parallel data/156-Mb/s serial data conversion and 156-Mb/s serial data transmission. In addition, it has a bit phase synchronizer and cell synchronizer, which enables it to transmit and synchronize serial data without a paralleled clock or a paralleled cell top signal, by distributing a common 156-MHz clock and a common cell top signal to the whole system. We evaluated the bit error rate and timing margin on data transmission under several conditions. The results show that we can apply this LSI to commercially available ATM switching systems. This paper also describes methods of expanding switch capacity and transmitting 624-Mb/s data using this LSI.