A 24-bit, 96 kHz stereo A/D converter (ADC) for DVD-audio has been developed. The single-chip integrates stereo delta-sigma modulators (Δ ΣM's), a voltage reference, and a decimation filter. A fourth-order cascaded Δ ΣM using a local feedback technique was employed to avoid overload without sacrificing noise performance. Low power switched-capacitor techniques were used for implementation. A two-stage decimation filter architecture that reduces digital switching noise was also developed. A merged multi-stage comb filter was used for the first stage, and a bit-serial finite-impulse-response (FIR) filter was used for the second stage. The 18.0 mm2 chip was fabricated in 0.6-µm CMOS with low threshold devices. Measured results show 117 dB A-weighted dynamic range in the 20 kHz passband, with 470 mW power dissipation at 5 V operation.

To improve measurement accuracy and speed, a switched-capacitor capacitance measurement circuit with the vernier scale is developed. Its process consists of a coarse measurement by charge-balancing A-D conversion and a fine measurement by single-slope A-D conversion. a prototype using discrete components confirms the principles of operation.

A cyclic analog-to-digital (A/D) converter is developed which accomplishes an n-b conversion in n/2 clock cycles. The architecture consists of two 1-b quantizers connected in a loop. A CMOS design of the 1-b quantizer is given to evaluate the performance of the A/D converter when implemented using presently available process. Spice simulations and error analyses show that a resolution higher than 10-b and a sampling rate up to 1.4 Msps are attainable with a 3-µm CMOS process. A prototype converter breadboarded using discrete components has confirmed the principles of operation and error analyses. The device count and the power consumption are small compared to those of a successive-approximation A/D converter. A chip area required for the CMOS implementation is also small because only four unit capacitors are involved. Therefore, the architecture proposed herein is most suited for high accuracy, medium speed A/D conversion.