This paper describes a new reduction mechanism of the stress induced leakage current that is induced by step tunneling of electrons through the step tunneling sites. The concept of this mechanism is based on the deactivation of step tunneling sites for thin oxide. It is verified that the deactivation is electrically realized by the injected electrons int the sites. It is because the step tunneling probability of electrons though the deactivated sites is suppressed, since the electron capture cross section of the neutralized deactivation sites becomes extremely low. The deactivation scheme is as follows: (1) The deactivation of tunneling sites can be realized that the tunneling sites trapped holes change to neutralized tunneling sites due to electrons injection. (2) The injected electron can deactivate the activation tunneling sites only under energy level than the energy level of the injected electrons. It is shown that the above reduction phenomenon can be quantifiably with formulation. These results are very important for high reliable thin oxide films and for high performance ULSI.

The increase of surface microroughness on Si substrate degrades the electrical characteristics such as the dielectric breakdown field intensity (EBD) and charge to break-down (QBD) of thin oxide film. It has been found that the surface microroughness increases in the wet chemical process, particularly in NH4OH-H2O2-H2O cleaning (APM cleaning). It has been revealed that the surface microroughness does not increase at all if the NH4OH mixing ratio in NH4OH-H2O2-H2O solution is reduced from the conventional level of 1:1:5 to 0.05:1:5, and the room temperature ultrapure water rinsing is introduced right after the APM cleaning. At the same time, the APM cleaning with NH4OH-H2O2-H2O mixing ratio of 0.05:1:5 has been very effective to remove particles and metallic impurities from the Si surface. The surface microroughness dominating the electrical properties of very thin oxide films is strictly influenced by the wafer quality. The increase of surface microroughness due to the APM cleaning has varied among the wafer types such as Cz, FZ and epitaxial (EPI) wafers. The increase of surface microroughness in EPI wafer was very much limited, while the surface microroughness of FZ and Cz wafers gradually increase. As a result of investigating the amount of diffused phosphorus atoms into these wafers, the increase of the surface microroughness in APM cleaning has been confirmed to strongly depend on the silicon vacancy cluster concentration in wafer. The EPI wafer having low silicon vacancy concentration is essentially revealed superior for future sub-half-micron ULSI devices.