The conventional bilateral motion estimation (BME) for motion-compensated frame rate up-conversion (MC-FRUC) can avoid the problem of overlapped areas and holes but usually results in lots of inaccurate motion vectors (MVs) since 1) the MV of an object between the previous and following frames is more likely to have no temporal symmetry with respect to the target block of the interpolated frame and 2) the repetitive patterns existing in video frame lead to the problem of mismatch due to the lack of the interpolated block. In this paper, a new BME algorithm with a low computational complexity is proposed to resolve the above problems. The proposed algorithm incorporates multi-resolution search into BME, since it can easily utilize the MV consistency between two adjacent pyramid levels and spatial neighboring MVs to correct the inaccurate MVs resulting from no temporal symmetry while guaranteeing low computational cost. Besides, the multi-resolution search uses the fast wavelet transform to construct the wavelet pyramid, which not only can guarantee low computational complexity but also can reserve the high-frequency components of image at each level while sub-sampling. The high-frequency components are used to regularize the traditional block matching criterion for reducing the probability of mismatch in BME. Experiments show that the proposed algorithm can significantly improve both the objective and subjective quality of the interpolated frame with low computational complexity, and provide the better performance than the existing BME algorithms.

A new technology for video frame rate up-conversion (FRUC) is presented by combining a median filter and motion estimation (ME) with an occlusion detection (OD) method. First, ME is performed to obtain a motion vector. Then, the OD method is used to refine the MV in the occlusion region. When occlusion occurs, median filtering is applied. Otherwise, bidirectional motion compensated interpolation (BDMC) is applied to create the interpolated frames. The experimental results show that the proposed algorithm provides better performance than the conventional approach. The average gain in the PSNR (Peak Signal to Noise Ratio) is always better than the other methods in the Full HD test sequences.

Novel joint motion-compensated interpolation using eight-neighbor block motion vectors (8J-MCI) is presented. The proposed method uses bi-directional motion estimation (BME) to obtain the motion vector field of the interpolated frame and adopts motion vectors of the interpolated block and its 8-neighbor blocks to jointly predict the target block. Since the smoothness of the motion vector filed makes the motion vectors of 8-neighbor blocks quite close to the true motion vector of the interpolated block, the proposed algorithm has the better fault-tolerancy than traditional ones. Experiments show that the proposed algorithm outperforms the motion-aligned auto-regressive algorithm (MAAR, one of the state-of-the-art frame rate up-conversion (FRUC) schemes) in terms of the average PSNR for the test image sequence and offers better subjective visual quality.

A method for spatio-temporal resolution enhancement of video sequences based on super-resolution reconstruction is proposed. A new observation model is defined for accurate resolution enhancement, which enables subpixel motion in intermediate frames to be obtained. A modified optimization formula for obtaining a high-resolution sequence is also adopted.

A low-voltage quadrature up-conversion CMOS mixer for 5-GHz wireless communication applications is designed with a TSMC 0.18-µm process. The fold-switching technique is used to implement the low-voltage double balanced quadrature mixer. A miniature lumped-element microwave broadband rat-race hybrid and RLC shift network are used for the local oscillator and the intermediate frequency port design, respectively. The measured results demonstrate that the mixer can reach a high conversion gain, a low noise figure (NF), and a high linearity. The mixer exhibits improvement in noise, conversion gain, and image rejection. The mixer shows a conversion gain of 16 dB, a noise figure of 12.8 dB, an image rejection of 45 dB, while dissipating 15.5 mW for an operating voltage at 1 V.

A low-power K-band CMOS current-mode up-conversion mixer is proposed. The proposed mixer is realized using four analog current-squaring circuits. This current-mode up-conversion mixer is fabricated in 0.13-µm 1P8M triple-well CMOS process, and has the measured power conversion gain of -5 dB. The fabricated CMOS up-conversion mixer dissipates only 3.1 mW from a 1-V supply voltage. The VCO can be tuned from 20.8 GHz to 22.7 GHz. Its phase noise is -108 dBc/Hz at 10-MHz offset frequency. It is shown that the proposed mixer has great potential for low-voltage and low-power CMOS transmitter front-ends in advanced nano-CMOS technologies.

This letter evaluates a transmitter architecture using harmonic images in D/A conversion for generating RF signals. In generating harmonic images, the problems such as intermodulation distortion of DAC were investigated. We developed an evaluation system with two bandpass filter and a buffer amplifier. It was experimentally found that the RF signal up to around 400 MHz can be generated by a commonly used 14-bit DAC at the sampling rates of around 40 MHz with EVM less than 6.6%. This letter also presents a more feasible transmitter example having an IF stage with harmonic image extraction scheme and a typical RF upconversion stage.

A fully integrated broadband up-conversion mixer with low power consumption is demonstrated on 90 nm CMOS technology in this paper. This mixer has a single-ended input and a multi-layer stacked Marchand balun is used for converting the differential output of the single-balanced mixer topology to a single-ended output. This balun employs inductive coupling between two metal layers and includes slotted shields to reduce substrate losses. The circuit size is 650 µm570 µm. At 22.1 GHz, the integrated mixer achieves a conversion gain of 2 dB with a maximum power dissipation of only 11.1 mW from a 1.2 V dc power supply at LO power of 5 dBm. Input referred 1-dB compression point is -14.8 dBm. The LO and RF return loss are better than 10 dB for frequencies between 20-26 GHz.