In this study, we consider the data compression with side information available at both the encoder and the decoder. The information source is assigned to a variable-length code that does not have to satisfy the prefix-free constraints. We define several classes of codes whose codeword lengths and error probabilities satisfy worse-case criteria in terms of side-information. As a main result, we investigate the exact first-order asymptotics with second-order bounds scaled as Θ(√n) as blocklength n increases under the regime of nonvanishing error probabilities. To get this result, we also derive its one-shot bounds by employing the cutoff operation.

The present study proposes a scheme in which variable-length orthogonal codes generated by combining inverse discrete Fourier transform matrices over a finite field multiplex user data into a multiplexed sequence and its sequence forms one or a plural number of codewords for Reed-Solomon coding. The proposed scheme realizes data multiplexing, error correction coding, and multi-rate transmitting at the same time. This study also shows a design example and its performance analysis of the proposed scheme.

The top-K sorting is a variant of sorting used heavily in applications such as database management systems. Recently, the use of field programmable gate arrays (FPGAs) to accelerate sorting operation has attracted the interest of researchers. However, existing hardware top-K sorting algorithms are either resource-intensive or of low throughput. In this paper, we present a resource-efficient top-K sorting architecture that is composed of L cascading sorting units, and each sorting unit is composed of P sorting cells. K=PL largest elements are produced when a variable length input sequence is processed. This architecture can operate at a high frequency while consuming fewer resources. The experimental results show that our architecture achieved a maximum 1.2x throughput-to-resource improvement compared to previous studies.

Sorting is one of the most fundamental problems in mathematics and computer science. Because high-throughput and flexible sorting is a key requirement in modern databases, this paper presents efficient techniques for designing a high-throughput sorting matrix that supports continuous data sequences. There have been numerous studies on the optimization of sorting circuits on FPGA (field-programmable gate array) platforms. These studies focused on attaining high throughput for a single command with fixed data width. However, the architectures proposed do not meet the requirement of diversity for database data types. A sorting matrix architecture is thus proposed to overcome this problem. Our design consists of a matrix of identical basic sorting cells. The sorting cells work in a pipeline and in parallel, and the matrix can simultaneously process multiple data streams, which can be combined into a high-width single-channel data stream or low-width multiple-channel data streams. It can handle continuous sequences and allows for sorting variable-length data sequences. Its maximum throughput is approximately 1.4 GB/s for 32-bit sequences and approximately 2.5 GB/s for 64-bit sequences on our platform.

This paper investigates the problem of variable-length intrinsic randomness for a general source. For this problem, we can consider two performance criteria based on the variational distance: the maximum and average variational distances. For the problem of variable-length intrinsic randomness with the maximum variational distance, we derive a general formula of the average length of uniform random numbers. Further, we derive the upper and lower bounds of the general formula and the formula for a stationary memoryless source. For the problem of variable-length intrinsic randomness with the average variational distance, we also derive a general formula of the average length of uniform random numbers.

We consider fixed-to-variable length coding with a regular cost function by allowing the error probability up to any constantε. We first derive finite-length upper and lower bounds on the average codeword cost, which are used to derive general formulas of two kinds of minimum achievable rates. For a fixed-to-variable length code, we call the set of source sequences that can be decoded without error the dominant set of source sequences. For any two regular cost functions, it is revealed that the dominant set of source sequences for a code attaining the minimum achievable rate under a cost function is also the dominant set for a code attaining the minimum achievable rate under the other cost function. We also give general formulas of the second-order minimum achievable rates.

A modular serial pipelined sorting architecture for continuous input sequences is presented. It supports continuous sequences, whose lengths can be dynamically changed, and does so using a very simple control strategy. It consists of identical serial cascaded sorting cells, and lends itself to high frequency implementation with any number of sorting cells, because both data and control signals are pipelined. With L cascaded sorting cells, it produces a fully sorted result for sequences whose length N is equal to or less than L+1; for longer sequences, the largest L elements are sorted out. Being modularly designed, several independent smaller sorters can be dynamically configured to form a larger sorter.

This paper introduces the concept of order complexity, which represents the minimum number of partial ordering operations to make a string of perfectly ordered symbols. A novel variable-length code expressing such order complexity using binary digits is proposed herein. The proposed code is general, uniquely decipherable, and useful for coding a string of random permuted symbols having unknown statistics or which are preferred to have a uniform distribution.

Test compression / decompression scheme for reducing the test application time and memory requirement of an LSI tester has been proposed. In the scheme, the employed coding algorithms are tailored to a given test data, so that the tailored coding algorithm can highly compress the test data. However, these methods have some drawbacks, e.g., the coding algorithm is ineffective in extra test data except for the given test data. In this paper, we introduce an embedded decompressor that is reconfigurable according to coding algorithms and given test data. Its reconfigurability can overcome the drawbacks of conventional decompressors with keeping high compression ratio. Moreover, we propose an architecture of reconfigurable decompressors for four variable-length codings. In the proposed architecture, the common functions for four codings are implemented as fixed (or non-reconfigurable) components so as to reduce the configuration data, which is stored on an ATE and sent to a CUT. Experimental results show that (1) the configuration data size becomes reasonably small by reducing the configuration part of the decompressor, (2) the reconfigurable decompressor is effective for SoC testing in respect of the test data size, and (3) it can achieve an optimal compression of test data by Huffman coding.

We propose an asynchronous variable-length optical packet switch that is based on a packet compression scheme and delay-line loop buffers, and evaluate the packet loss probability of the proposed switch through simulation and analysis. Simulation results well the analytical results and show the accuracy of our analysis. When the packet compression ratio is low, optical packet interval regulators are useful to improve the packet loss probability characteristics.

In this letter, we generalize the achievability of variable-length coding from two viewpoints. One is the definition of an overflow probability, and the other is the definition of an achievability. We define the overflow probability as the probability of codeword length, not per symbol, is larger than ηn and we introduce the ε-achievability of variable-length codes that implies an existence of a code for the source under the condition that the overflow probability is smaller than or equal to ε. Then we show that the ε-achievability of variable-length codes is essentially equivalent to the ε-achievability of fixed-length codes for general sources. Moreover by using above results, we show the condition of ε-achievability for some restricted sources given ε.

A 128128 pixel functional image sensor was implemented. The sensor was able to capture images at 1,000 frame/s and extract the sizes and positions of 10 objects/frame when clocked at 8 MHz. The size of each pixel was 18 µm18 µm and the fill factor was 28%. The chip, 3.24 mm3.48 mm in size, was implemented with a 0.35 µm CMOS sensor process; the power consumption was 29.7 mW at 8 MHz.

Test compression / decompression using variable-length coding is an efficient method for reducing the test application cost, i.e., test application time and the size of the storage of an LSI tester. However, some coding techniques impose slow test application, and consequently a large test application time is required despite the high compression. In this paper, we clarify the fact that test application time depends on the compression ratio and the length of codewords and then propose a new Huffman-based coding method for achieving small test application time in a given test environment. The proposed coding method adjusts both of the compression ratio and the minimum length of the codewords to the test environment. Experimental results show that the proposed method can achieve small test application time while keeping high compression ratio.

Many image and video compression algorithms work by splitting the image into blocks and producing variable-length code bits for each block data. If variable-length code data are transmitted consecutively over error-prone channel without any error protection technique, the receiving decoder cannot decode the stream properly. So the standard image and video compression algorithms insert some redundant information into the stream to provide some protection against channel errors. One of such redundancy is resynchronization marker, which enables the decoder to restart the decoding process from a known state in the event of transmission errors, but its frequent use should be restricted not to consume bandwidth too much. The Error Resilient Entropy Code (EREC) is well known method which can regain synchronization without any redundant information. It can work with the overall prefix codes, which many image compression methods use. This paper proposes an improvement to FEREC (Fast Error-Resilient Entropy Coding). It first calculates initial searching position according to bit lengths of consecutive blocks. Second, initial offset is decided using statistical distribution of long and short blocks, and initial offset is adjusted to insure all possible offset value can be examined. The proposed algorithm can speed up the construction of EREC slots, and can preserve compressed image quality in the event of transmission errors. The simulation result shows that the quality of transmitted image is enhanced about 0.3-3.5 dB compared with the existing FEREC when random channel error happens.

We study photonic packet switches to support asynchronously arriving variable-length packets. A scheduler for contention resolution is operated in electrical domain even when data street of the buffer is provided in optical domain. In this scheme, the scheduler may be a bottleneck. To compensate the gap of high-speed optical transmission and slow-speed electronic processing, we propose a multi-stage fiber delay line (FDL) buffer architecture that forms a tree structure in which each node has a block of FDLs and a scheduler. This is especially useful for output-buffer switches in which scheduling complexity is proportional to the number of ports of the packet switch. Through a newly-developed approximate analytical method, we show the optimum unit length of the fiber delay lines to decrease packet loss probability. We also show the sufficient number of FDLs in the two-stage buffer.

In variable-length coding, the probability of codeword length per source letter being above (resp. below) a prescribed threshold is called the overflow (resp. the underflow) probability. In this paper, we show that the infimum achievable threshold given the overflow probability exponent r always coincides with the infimum achievable fixed-length coding rate given the error exponent r, without any assumptions on the source. In the case of underflow probability, we also show the similar results. From these results, we can utilize various theorems and results on the fixed-length coding established by Han for the analysis of overflow and underflow probabilities. Moreover, we generalize the above results to the case with overflow and underflow probabilities of codeword cost.

This paper proposes and evaluates a character or symbol code system called EPICS for multilingual information processing. EPICS integrates a variable-length coding system using 16-bit units and a smart virtual machine. EPICS enhances the interchangeability of data. The variable-length coding system provides a huge code space. This huge space can include not only standardized code sets but also non-standardized codes of ancient symbols and user-specific symbols. The smart virtual machine executes inputs as instructions and is dynamically customizable. It allows us to define and modify instructions during runtime and provides us with customization facilities. Customization facilities can be used to specify a sorting order and normalization. Customization also makes it possible for an information producer (sender) to express his intentions or annotations in data and for an information consumer (receiver) to process the data depending on his needs. Moreover, customization enables one to send compressed data and decompression program fragments incrementally and efficiently without predefined decompression algorithms.

Moving-picture transmission through narrow band and high bit error rate communication channels, such as a mobile communication channel, requires improved compression rate and enhanced error resilience. Variable-length codes are one of the essential techniques of compressing digital video information. This technique is used in various video coding schemes although a bit error in the channel impairs the synchronization of variable-length codewords, resulting in propagation of the error. With a hybrid video coding method in particular, which combines motion-compensation and transform coding, once an error is detected in the coded data, subsequent data cannot be decoded. Consequently, even an error-free portion of any data received must be discarded. To minimize the influence of an error in a channel on coded video data, this paper proposes a new video coding syntax which makes the best use of the self synchronizing characteristic of variable-length Huffman codes. Owing to the Huffman code's characteristic, the proposed coding syntax enables a decoder to decode the data portion that cannot be decoded, due to an error, by the conventional syntax without adding any redundancy. Computer simulation has verified the effectiveness of this proposed syntax in video coding with a very low bitrate and erroneous communication channel.

In our recent work, a forward test generation method for sequential circuits by using a single time frame was proposed. In order to improve the effectiveness of the method, we introduced an extended mode which can handle the two time frames for a hard-to-test fault and a state escaping phase which can detect a sequence of unsuitable states for test generation. The experimental results show that the improved method is effective in generating higher coverage tests with a small number of tests.