High Resolution and Fast Frequency Settling PLL Synthesizer

Kazuhiko SEKI; Masahiro MORIKURA; Shuzo KATO

High Resolution and Fast Frequency Settling PLL Synthesizer

Kazuhiko SEKI, Masahiro MORIKURA, Shuzo KATO

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This paper proposes a high resolution and fast frequency settling PLL synthesizer for frequency hopping radio communication equipment. The proposed synthesizer enables the carrier frequency to be changed within the duration of a burst signal and yields higher frequency resolution than the reference signal frequency. To reduce frequency settling time without degradation of frequency resolution and phase noise, this paper proposes a new phase and frequency preset (PEP) PLL synthesizer which employs a digital phase accumulator to generate high resolution reference signal. Experimental results show that the settling time of a prototype synthesizer is less than 300µs while spurious signals are suppressed by more than 55 dB. In comparison with conventional PLL synthesizers, the frequency settling time is reduced by 80%. Furthermore, the higher frequency resolution than the reference signal is successfully demonstrated. Therefore, the proposed PFP PLL synthesizer with the digital reference signal can achieve the output signal with high frequency resolution less than 1Hz.

Publication: IEICE TRANSACTIONS on Communications Vol.E75-B No.8 pp.739-746

Publication Date: 1992/08/25

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Type of Manuscript: Special Section PAPER (Special Issue on the 4th Japan-Korea Joint Conference on Communications, Networks, Switching Systems and Satellite Communications (4th JC-CNSS))

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Kazuhiko SEKI, Masahiro MORIKURA, Shuzo KATO, "High Resolution and Fast Frequency Settling PLL Synthesizer" in IEICE TRANSACTIONS on Communications, vol. E75-B, no. 8, pp. 739-746, August 1992, doi: .
Abstract: This paper proposes a high resolution and fast frequency settling PLL synthesizer for frequency hopping radio communication equipment. The proposed synthesizer enables the carrier frequency to be changed within the duration of a burst signal and yields higher frequency resolution than the reference signal frequency. To reduce frequency settling time without degradation of frequency resolution and phase noise, this paper proposes a new phase and frequency preset (PEP) PLL synthesizer which employs a digital phase accumulator to generate high resolution reference signal. Experimental results show that the settling time of a prototype synthesizer is less than 300µs while spurious signals are suppressed by more than 55 dB. In comparison with conventional PLL synthesizers, the frequency settling time is reduced by 80%. Furthermore, the higher frequency resolution than the reference signal is successfully demonstrated. Therefore, the proposed PFP PLL synthesizer with the digital reference signal can achieve the output signal with high frequency resolution less than 1Hz.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e75-b_8_739/_p

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@ARTICLE{e75-b_8_739,
author={Kazuhiko SEKI, Masahiro MORIKURA, Shuzo KATO, },
journal={IEICE TRANSACTIONS on Communications},
title={High Resolution and Fast Frequency Settling PLL Synthesizer},
year={1992},
volume={E75-B},
number={8},
pages={739-746},
abstract={This paper proposes a high resolution and fast frequency settling PLL synthesizer for frequency hopping radio communication equipment. The proposed synthesizer enables the carrier frequency to be changed within the duration of a burst signal and yields higher frequency resolution than the reference signal frequency. To reduce frequency settling time without degradation of frequency resolution and phase noise, this paper proposes a new phase and frequency preset (PEP) PLL synthesizer which employs a digital phase accumulator to generate high resolution reference signal. Experimental results show that the settling time of a prototype synthesizer is less than 300µs while spurious signals are suppressed by more than 55 dB. In comparison with conventional PLL synthesizers, the frequency settling time is reduced by 80%. Furthermore, the higher frequency resolution than the reference signal is successfully demonstrated. Therefore, the proposed PFP PLL synthesizer with the digital reference signal can achieve the output signal with high frequency resolution less than 1Hz.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - High Resolution and Fast Frequency Settling PLL Synthesizer
T2 - IEICE TRANSACTIONS on Communications
SP - 739
EP - 746
AU - Kazuhiko SEKI
AU - Masahiro MORIKURA
AU - Shuzo KATO
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E75-B
IS - 8
JA - IEICE TRANSACTIONS on Communications
Y1 - August 1992
AB - This paper proposes a high resolution and fast frequency settling PLL synthesizer for frequency hopping radio communication equipment. The proposed synthesizer enables the carrier frequency to be changed within the duration of a burst signal and yields higher frequency resolution than the reference signal frequency. To reduce frequency settling time without degradation of frequency resolution and phase noise, this paper proposes a new phase and frequency preset (PEP) PLL synthesizer which employs a digital phase accumulator to generate high resolution reference signal. Experimental results show that the settling time of a prototype synthesizer is less than 300µs while spurious signals are suppressed by more than 55 dB. In comparison with conventional PLL synthesizers, the frequency settling time is reduced by 80%. Furthermore, the higher frequency resolution than the reference signal is successfully demonstrated. Therefore, the proposed PFP PLL synthesizer with the digital reference signal can achieve the output signal with high frequency resolution less than 1Hz.
ER -