IEICE TRANSACTIONS on Electronics
A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs
Summary :
A wide-range multiphase delay-locked loop (DLL) using mixed-mode voltage-controlled delay lines (VCDLs) is presented. An edge-triggered duty cycle corrector is introduced to generate output clocks with 50% duty cycle. This DLL using an analog 3-states phase-frequency detector (PFD) and the proposed digital PFD can achieve low jitter operation over a wide frequency range without harmonic locking problems. It has been fabricated in a standard 0.25-µm CMOS technology and occupies a core area of 1 mm2 including the on-chip regulator and loop filter. For reference clocks from 20 MHz to 550 MHz, all the measured rms and peak-to-peak jitters are below 10 ps and 78 ps, respectively.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.6 pp.1248-1252
- Publication Date
- 2005/06/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.6.1248
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
- Category
- PLL
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Rong-Jyi YANG, Shen-Iuan LIU, "A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 6, pp. 1248-1252, June 2005, doi: 10.1093/ietele/e88-c.6.1248.
Abstract: A wide-range multiphase delay-locked loop (DLL) using mixed-mode voltage-controlled delay lines (VCDLs) is presented. An edge-triggered duty cycle corrector is introduced to generate output clocks with 50% duty cycle. This DLL using an analog 3-states phase-frequency detector (PFD) and the proposed digital PFD can achieve low jitter operation over a wide frequency range without harmonic locking problems. It has been fabricated in a standard 0.25-µm CMOS technology and occupies a core area of 1 mm2 including the on-chip regulator and loop filter. For reference clocks from 20 MHz to 550 MHz, all the measured rms and peak-to-peak jitters are below 10 ps and 78 ps, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.6.1248/_p
Copy
@ARTICLE{e88-c_6_1248,
author={Rong-Jyi YANG, Shen-Iuan LIU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs},
year={2005},
volume={E88-C},
number={6},
pages={1248-1252},
abstract={A wide-range multiphase delay-locked loop (DLL) using mixed-mode voltage-controlled delay lines (VCDLs) is presented. An edge-triggered duty cycle corrector is introduced to generate output clocks with 50% duty cycle. This DLL using an analog 3-states phase-frequency detector (PFD) and the proposed digital PFD can achieve low jitter operation over a wide frequency range without harmonic locking problems. It has been fabricated in a standard 0.25-µm CMOS technology and occupies a core area of 1 mm2 including the on-chip regulator and loop filter. For reference clocks from 20 MHz to 550 MHz, all the measured rms and peak-to-peak jitters are below 10 ps and 78 ps, respectively.},
keywords={},
doi={10.1093/ietele/e88-c.6.1248},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1248
EP - 1252
AU - Rong-Jyi YANG
AU - Shen-Iuan LIU
PY - 2005
DO - 10.1093/ietele/e88-c.6.1248
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2005
AB - A wide-range multiphase delay-locked loop (DLL) using mixed-mode voltage-controlled delay lines (VCDLs) is presented. An edge-triggered duty cycle corrector is introduced to generate output clocks with 50% duty cycle. This DLL using an analog 3-states phase-frequency detector (PFD) and the proposed digital PFD can achieve low jitter operation over a wide frequency range without harmonic locking problems. It has been fabricated in a standard 0.25-µm CMOS technology and occupies a core area of 1 mm2 including the on-chip regulator and loop filter. For reference clocks from 20 MHz to 550 MHz, all the measured rms and peak-to-peak jitters are below 10 ps and 78 ps, respectively.
ER -
English
